JPS6022821B2 - semiconductor equipment - Google Patents
semiconductor equipmentInfo
- Publication number
- JPS6022821B2 JPS6022821B2 JP52087388A JP8738877A JPS6022821B2 JP S6022821 B2 JPS6022821 B2 JP S6022821B2 JP 52087388 A JP52087388 A JP 52087388A JP 8738877 A JP8738877 A JP 8738877A JP S6022821 B2 JPS6022821 B2 JP S6022821B2
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- wire
- emitter
- wires
- lead
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W44/00—Electrical arrangements for controlling or matching impedance
- H10W44/20—Electrical arrangements for controlling or matching impedance at high-frequency [HF] or radio frequency [RF]
- H10W44/203—Electrical connections
- H10W44/206—Wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/075—Connecting or disconnecting of bond wires
- H10W72/07551—Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/075—Connecting or disconnecting of bond wires
- H10W72/07551—Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting
- H10W72/07554—Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting changes in dispositions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/531—Shapes of wire connectors
- H10W72/536—Shapes of wire connectors the connected ends being ball-shaped
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/531—Shapes of wire connectors
- H10W72/5363—Shapes of wire connectors the connected ends being wedge-shaped
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/541—Dispositions of bond wires
- H10W72/5453—Dispositions of bond wires connecting between multiple bond pads on a chip, e.g. daisy chain
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/541—Dispositions of bond wires
- H10W72/547—Dispositions of multiple bond wires
- H10W72/5475—Dispositions of multiple bond wires multiple bond wires connected to common bond pads at both ends of the wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/59—Bond pads specially adapted therefor
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
- H10W72/931—Shapes of bond pads
- H10W72/932—Plan-view shape, i.e. in top view
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink
Landscapes
- Wire Bonding (AREA)
Description
【発明の詳細な説明】
本発明は半導体装置に関するもので、高周波高出力トラ
ンジスタを対象とするものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and is directed to a high frequency, high output transistor.
高周波特性がよく電流容量が大なる高周波高出力トラン
ジスタを得るには、半導体基板から取り出す電極の抵抗
を充分に小さくしなければならない。半導体基板からの
電極取り出し抵抗を減少させる手段として従釆、金属蝿
極の膜厚を厚くするか、又は第1図aに示すように同電
位電極パットを二箇所以上配置しそれら電極パット間を
接続する電極接続片部の幅Qを広く取るようにするか、
あるいは二箇所以上ある同電位電極パットとりード間を
ワイヤで相互に接続する方法が採られた。In order to obtain a high frequency, high output transistor with good high frequency characteristics and a large current capacity, the resistance of the electrode taken out from the semiconductor substrate must be made sufficiently small. As a means to reduce the resistance of the electrodes taken out from the semiconductor substrate, it is necessary to increase the film thickness of the metal fly electrode, or to arrange two or more electrode pads with the same potential as shown in Fig. Either increase the width Q of the electrode connection piece to be connected, or
Alternatively, a method has been adopted in which two or more electrode pads and leads of the same potential are interconnected with wires.
しかしながらいずれの場合にも以下に述べるような欠点
がある。【11 金属(Aそ)電極の膜厚を厚くする場
合は、金属(Aそ)電極を形成するホトェッチングのと
きに、蒸着金属膜が横長に斜視してホトェッチソグの誤
差が大きくなるために、電極加工歩留りが低下し、した
がって、高周波特性に優れ、電流容量の大きな高周波高
出力トランジスタが得られにくい。However, in either case, there are drawbacks as described below. [11] When increasing the film thickness of the metal (A) electrode, during photoetching to form the metal (A) electrode, the vapor-deposited metal film becomes obliquely oblong, increasing the error in photoetching. Processing yield is reduced, and therefore, it is difficult to obtain a high frequency, high output transistor with excellent high frequency characteristics and large current capacity.
{21 第1図aを参照し電極接続片部の幅Qを広くす
る場合は、寄生MOS容量が大きくなり、そのために高
周波特性が悪化する。{21 Referring to FIG. 1a, if the width Q of the electrode connection piece is increased, the parasitic MOS capacitance increases, which deteriorates the high frequency characteristics.
また、電極接続片部の幅を広くするとそれにともなって
第1図aに示すように、半導体基板全体を大きくなるた
めに原価高となる。Further, if the width of the electrode connection piece is increased, the overall size of the semiconductor substrate becomes larger as shown in FIG. 1A, resulting in an increase in cost.
{3} 第1図a,bに示すように、同一電極の二個以
上の電極パットとりード間を複数のワイヤで直接接続す
る場合は、ワイヤが長く、かつ複数のワイヤが複雑に入
り組むため、タブショート及び他の電極ワイヤとの接触
が起り、そのために、信頼性に欠ける。{3} As shown in Figure 1 a and b, when connecting two or more electrode pads and leads of the same electrode directly with multiple wires, the wires are long and complicated. Because of the assembly, tab shorts and contact with other electrode wires can occur, making them unreliable.
このように、従来の手段による場合には種々の欠点があ
った。As described above, the conventional means have various drawbacks.
本発明はかかる欠点を解消するためになされたもので、
したがって、本発明の目的は‘11、電極加工歩留りを
向上させ、高周波特性の優れた電流容量の大なる高周波
高出力半導体装置を容易に得ること、■寄生MOS容量
を少なくし、高周波特性の向上を図るとともに、半導体
基板の小型化を図ることによって高周波高出力半導体装
置の原価低減を図ること、‘3汐ブショート及び他の鱒
極ワイヤとの接触を少〈して、高周波高出力半導体装置
の信頼性の向上を図ることにある。The present invention has been made to eliminate such drawbacks,
Therefore, the purpose of the present invention is to improve the electrode processing yield and easily obtain a high-frequency, high-output semiconductor device with excellent high-frequency characteristics and large current capacity; (1) to reduce parasitic MOS capacitance and improve high-frequency characteristics; At the same time, we aim to reduce the cost of high-frequency, high-power semiconductor devices by downsizing the semiconductor substrate, and reduce the contact with the '3-shio shorts and other wires to improve the production of high-frequency, high-power semiconductor devices. The purpose is to improve reliability.
以下本発明を詳細に説明する。The present invention will be explained in detail below.
第2図は本発明の高周波高出力トランジスタの一実施例
を示すものである。FIG. 2 shows an embodiment of the high frequency, high output transistor of the present invention.
同図において、1はシリコン半導体基板で金メッキした
金属タブ2にAu−Si共晶合金接合等によって固定さ
れる。In the figure, a silicon semiconductor substrate 1 is fixed to a gold-plated metal tab 2 by Au--Si eutectic alloy bonding or the like.
この半導体基板1には中央部に2仏厚のAそベース電極
3及びその周囲に同じく2〃のAクェミッタ亀極4a,
4bが配設されている。電流が多く流れないベース電極
3側はその中央に1つのベース電極パット5が設けられ
、このベース電極パット5と半導体基板1の外側に配置
されたベースリード6との間が40〃◇のAu線からな
るワイヤ7で直接接続されている。This semiconductor substrate 1 has an A base electrode 3 with a thickness of 2 cm in the center, and a 2 cm A quamitter Kame electrode 4a around it.
4b is arranged. One base electrode pad 5 is provided in the center of the base electrode 3 side where a large current does not flow, and the distance between this base electrode pad 5 and the base lead 6 arranged on the outside of the semiconductor substrate 1 is 40〃◇ Au. They are directly connected by a wire 7 consisting of a wire.
電流が多く流れるェミッタ電極4a,4b側は、両部分
にそれぞれ二つのェミッタ電極パット8a,8b及び8
c,8dが設けられ、まず向き合っている(隔離されて
いる)電極パット8a,8c間及び8b,8a間が40
仏?のAu線からワイヤ9a,9bによりそれぞれ接続
され、次に半導体基板1の外側に配置されたヱミツタリ
ード10と電極パット間がなるべく短かし、距離で接続
しえるように、リード側にある電極パット8cとェミッ
タリード10及び電極パット8aとヱミッタリード10
間を40〃めのAu線からなるワイヤ11a,1 1b
で接続されている。Two emitter electrode pads 8a, 8b and 8 are provided on both sides of the emitter electrodes 4a and 4b, through which a large amount of current flows.
First, there are 40 electrode pads between facing (separated) electrode pads 8a and 8c and between 8b and 8a.
Buddha? The Au wires are connected by wires 9a and 9b, respectively, and then the electrode pads on the lead side are connected to the emitter lead 10 arranged on the outside of the semiconductor substrate 1 so that the distance between the electrode pads is as short as possible and the distance between them is connected. 8c and emitter lead 10 and electrode pad 8a and emitter lead 10
Wires 11a, 11b made of Au wire with 40th wire between them
connected with.
このような高周波高出力トランジスタによれば、電流が
多く流れるェミツタ電極の電極パットを複数個隔離して
設け、その間をワイヤで接続する。According to such a high-frequency, high-output transistor, a plurality of electrode pads of the emitter electrode through which a large amount of current flows are provided in isolation, and the electrode pads are connected with a wire.
.この結果、電極パット間を接続する電極接続片部がほ
とんどなくなり寄生MOS容量が4・さくなり、そのた
めに、高周波特性が良好となる。.. As a result, there are almost no electrode connection pieces connecting the electrode pads, and the parasitic MOS capacitance is reduced by 4.degree., thereby improving high frequency characteristics.
また、電極接続片部の幅を4・さくし、又はそれを〈す
ことができるから、その結果半導体基板の小型化が図れ
、高周波高出力トランジスタの原価低減が図れるもので
ある。さらに、本発明によれば、ェミッタ電極パットと
ェミツタリードとの間を接続するのに、なるべく短かし
・距離でワイヤ接続するようにリード側にある電極パッ
トとりードとを接続している。Furthermore, since the width of the electrode connection piece can be reduced by 4 mm, the semiconductor substrate can be made smaller, and the cost of the high-frequency, high-output transistor can be reduced. Further, according to the present invention, when connecting the emitter electrode pad and the emitter lead, the electrode pad on the lead side is connected to the lead so that the wire connection is made as short as possible.
こうすると、ワイヤは短か〈なり、かつ複雑に入り組む
ことがなくなる。したがって、タブショート及び他の電
極ワイヤとの接触は少なくなり、信頼性の高い半導体装
置が得られる。なお、本発明によれば、亀極取出し薮抗
を減すために、金属電極の膜厚を特別厚くする必要がな
いから、ホトェツチングの誤差が小さく、電極加工歩留
が向上する。This way, the wires will be shorter and less complicated. Therefore, tab shorts and contact with other electrode wires are reduced, resulting in a highly reliable semiconductor device. According to the present invention, it is not necessary to make the thickness of the metal electrode particularly thick in order to reduce the thickness of the metal electrode, so that the photoetching error is small and the electrode processing yield is improved.
したがって、高周波特性の優れた電流容量の大きな高周
波高出力トランジスタが容易に得られる。上記実施例に
おいては、ベース電極の電極パットを1個とし、ェミツ
夕電極の電極パットを4個としたが、必要に応じてベー
ス電極パットを2個以上設け、電極パット相互間をワイ
ヤで接続し半導体基板1の外側に配設されたベースリー
ド6と接続し、ェミッ夕電極の電極パットも適当な数に
し、電極パット相互間をワイヤで接続し、ェミッタリー
ド10と近接する対応電極パット間をワイヤで接続する
ようにしてもよい。Therefore, a high frequency, high output transistor with excellent high frequency characteristics and large current capacity can be easily obtained. In the above embodiment, the base electrode has one electrode pad and the emitter electrode has four electrode pads, but if necessary, two or more base electrode pads can be provided and the electrode pads can be connected with wires. The emitter lead 10 is connected to the base lead 6 disposed on the outside of the semiconductor substrate 1, the emitter electrode has an appropriate number of electrode pads, the electrode pads are connected with wires, and the emitter lead 10 is connected to the adjacent corresponding electrode pad. It may also be connected by wire.
また、上記実施例においては、ェミツタ電極側のワイヤ
接続を、電極パット相互間のワイヤ接続とェミッタリー
ドと近接するェミッタ電極パット間のワイヤ接続を別々
のワイヤで接続したが、本発明は、ェミッタ電極パット
相互間のワイヤ接続とェミツタリードと近接するェミッ
タ電極パット間のワイヤ接続を切らずに一本のワイヤで
接続する手段を採用してもよい。Furthermore, in the above embodiment, the wire connection on the emitter electrode side was made using separate wires for the wire connection between the electrode pads and the wire connection between the emitter lead and the adjacent emitter electrode pad, but in the present invention, the emitter electrode It is also possible to adopt a means of connecting the pads with a single wire without cutting the wire connection between the pads and the wire connection between the emitter lead and the adjacent emitter electrode pad.
本発明は、高周波高出力トランジスタの如く大電流を流
しかつ高周波特性を損なわないように抵抗を小さくし静
電容量を小さくする必要があるパワーIC(集積回路装
置)、その他の半導体装置に有効である。The present invention is effective for power ICs (integrated circuit devices) and other semiconductor devices such as high-frequency, high-output transistors that flow large currents and require low resistance and low capacitance so as not to impair high-frequency characteristics. be.
第1図は従来の高周波高出力トランジスタの一実施例を
示すもので、aは平面図、bはその正面図、第2図は本
発明の高周波高出力トランジスタの一実施例を示すもの
で、aは平面図、bはその正面図である。
1・・・半導体基板、2・・・タブ、3・・・A夕べー
ス電極、Aa,Ab・・・Aクェミッタ電極、5・・・
ベース電極パット、6…ベースリード、7…9a,9b
、11a,11b,ワイヤ、8a,8b、8a,8d…
ェミッタ電パット、10…ェミッタリード。
第1図第2図FIG. 1 shows an embodiment of a conventional high frequency, high power transistor, in which a is a plan view, b is a front view thereof, and FIG. 2 is an embodiment of a high frequency, high power transistor of the present invention. A is a plan view, and b is a front view thereof. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2... Tab, 3... A base electrode, Aa, Ab... A quamitter electrode, 5...
Base electrode pad, 6...Base lead, 7...9a, 9b
, 11a, 11b, wire, 8a, 8b, 8a, 8d...
Emitter electric pad, 10...Emitter lead. Figure 1 Figure 2
Claims (1)
複数の電極パツトを配置し各電極パツトと対応リード間
をそれぞれワイヤで接続してなる半導体装置において、
上記電極のうち少なくとも電流が多く流れかつ互に同電
位の電極パツトを上記半導体素子を挟んで両側に互に隔
離して配置し、上記同電位の電極パツト相互間を第1の
ワイヤで接続し、対応リードに近い方の電極パツトと上
記対応リードとを第2のワイヤで接続するようにしてな
り、さらに電流が上記より少なく流れる電極パツトとそ
れに対応するリード間を上記第1のワイヤの上方をそれ
とクロスして第3のワイヤで接続してなることを特徴と
する半導体装置。1. In a semiconductor device in which a semiconductor element part and a plurality of corresponding electrode parts are arranged on a semiconductor substrate, and each electrode part and the corresponding lead are connected by wires,
Among the electrodes, at least the electrode parts through which a large current flows and are at the same potential are arranged in isolation from each other on both sides with the semiconductor element in between, and the electrode parts having the same potential are connected by a first wire. , the electrode pad closer to the corresponding lead and the corresponding lead are connected by a second wire, and a wire is connected above the first wire between the electrode pad through which less current flows than the corresponding lead and the corresponding lead. A semiconductor device, characterized in that the semiconductor device is formed by crossing the first wire and connecting the second wire with a third wire.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP52087388A JPS6022821B2 (en) | 1977-07-22 | 1977-07-22 | semiconductor equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP52087388A JPS6022821B2 (en) | 1977-07-22 | 1977-07-22 | semiconductor equipment |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5422768A JPS5422768A (en) | 1979-02-20 |
| JPS6022821B2 true JPS6022821B2 (en) | 1985-06-04 |
Family
ID=13913499
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP52087388A Expired JPS6022821B2 (en) | 1977-07-22 | 1977-07-22 | semiconductor equipment |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6022821B2 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6260003U (en) * | 1985-10-02 | 1987-04-14 | ||
| JPS6265804U (en) * | 1985-10-16 | 1987-04-23 | ||
| JPH0373421U (en) * | 1989-07-20 | 1991-07-24 | ||
| WO2018189948A1 (en) * | 2017-04-12 | 2018-10-18 | 三菱電機株式会社 | Semiconductor module, method for manufacturing semiconductor module, and power conversion apparatus |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP7624913B2 (en) * | 2021-11-25 | 2025-01-31 | 三菱電機株式会社 | Semiconductor Device |
-
1977
- 1977-07-22 JP JP52087388A patent/JPS6022821B2/en not_active Expired
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6260003U (en) * | 1985-10-02 | 1987-04-14 | ||
| JPS6265804U (en) * | 1985-10-16 | 1987-04-23 | ||
| JPH0373421U (en) * | 1989-07-20 | 1991-07-24 | ||
| WO2018189948A1 (en) * | 2017-04-12 | 2018-10-18 | 三菱電機株式会社 | Semiconductor module, method for manufacturing semiconductor module, and power conversion apparatus |
| JP6410998B1 (en) * | 2017-04-12 | 2018-10-24 | 三菱電機株式会社 | Semiconductor module, semiconductor module manufacturing method, and power conversion device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5422768A (en) | 1979-02-20 |
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