JPS6022823A - Switching pulse generation circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to the generation of switching pulses for switching a plurality of input signals, such as with an analogue switcher.

Conventional configuration and its problems In recent years, television receivers have been equipped with multiple video inputs: 1.゛.

It has a child, which can be changed sequentially from LJJ to LJJ by remote control. One way to do this is to
For example, you can have 3 to 5 input terminals, and use a remote control or a switch on the receiver to switch input terminals in sequence, such as input 1, input 2, manual input 3, etc., each time you press a button. It is being done.

However, the drawback of this method is that once the number of input terminal pieces increases, the button must be pressed many times to return to the original state.・For example, even if signals are supplied only to input 1 and input 2, switching from input 1 to input 2 can be done with one button operation, but when switching to input 1 next time, d:, 3, 4...
・After pressing n several times, there are 8 lines even though it is input 1, and the operability becomes extremely poor.

OBJECTS OF THE INVENTION The present invention aims to eliminate such drawbacks by providing a circuit that can automatically skip over input terminals other than those to which an input signal is supplied. It is something.

Structure of the Invention The switching pulse generating device according to the present invention includes a counter and a decoder, and is provided with an electronic switching circuit that sequentially switches the large scale signal each time a clock pulse is applied to the counter, and delays and differentiates the output pulse of the decoder. A logic gate is formed between the signal and the output of a mechanical switch linked to the input terminal according to the input signal supplied to the input terminal, and the clock input of the counter is returned to the clock input of the counter.If the connector is not connected to the input terminal, the counter counts. This is a skip operation that moves forward.

Fig. 1 shows -ψ of the switching pulse generation circuit according to an embodiment of the present invention.
1) is a block diagram.

The switching circuit 1 is made up of n analog switches corresponding to the number of input elements. The input terminal is equipped with an interlocking switch, and when the input terminal (C) is inserted, switches 81 to Sn become ovens.Generally, the phono pin type is well known.Switch 81 ~ One terminal of Sn is connected to each detection circuit 21 to 2
connected to n.

The switching pulse generator that controls the analog switch consists of an n-ary counter 3 and a binary 10 that decodes it.
It consists of a hexadecimal decoder 4. A forward pulse from a remote controller or the like is applied to the clock input of the n-ary counter 3 via a differential circuit 5 and an OR gate 6.

On the other hand, each output of the decoder 4 is connected to each analog SW, and at the same time, is also connected to the detection circuits 21 to 2n.

The detection circuits 2l-2n have input terminals connected to switches 81 to Sn.
It is detected whether or not the input is connected to that terminal based on the state of The pulse is applied to the clock input of the counter 3 via the OR gate 6 to advance the count of the counter 3 by one place. The detection circuits 21 to 2n have n detection circuits corresponding to the number of input circuits, and their outputs are combined by an OR gate 6 and connected to a clock input terminal of an n-ary counter 3. Detection circuits 21 to 2 in FIG. 2 and FIG.
The output of the 0 decoder 4 is given a slight delay by R1 and C1 and is added to the buffer input of IC1+.The output of OrG++ is R2, 02, IC+2. The rising part is detected by a logic differentiator circuit composed of IC+3, and the AND
Appears in the output of gate I C+3 (I(/ from Sl)
When the input to 13 is at a high level (when the equal input terminal is not connected).

A switch linked to the input terminal is connected to C13, and only when the switch output is H'', A of I Cas is connected.
The 0 switch, which provides a detection output at the ND gate output, is configured to be at a high level only when the corresponding input terminal is open.

IGla is an OR gate for the outputs of the detection circuits 21 to 2n.

FIG. 4 shows an example of the operation of the above-described configuration, and shows a case where the input terminal 1 is initially input and the forward pulse is input 11. At this time, it is assumed that the input terminal 2 is not connected to the terminal ← and the input terminal 3 is connected.

The forward pulse is detected by the logic differentiator circuit 6 at the rising edge.
Added to counter 3 clock input.

Initially, the output "0" of the decoder 4 is at a high level, but at the falling edge of the clock, the state changes and the decoder output 1 becomes a high level. Then, the output appears in the detection circuit 2 and is added to the counter clock input, so that the state transitions and the decoder output becomes one digit low level, and the decoder output 2 reaches a high level.

As described above, it is possible to configure a switching pulse generation circuit that skips terminals to which inputs are not connected.

Effects of the Invention As described above, according to the present invention, when switching a plurality of inputs sequentially, if an output pin is not connected to an input terminal, that input terminal automatically changes to 41 (and then automatically switches to the next input terminal). By switching to , it is possible to obtain a switching device with good operability.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a switching pulse generator according to an embodiment of the present invention, FIG. 2 is a circuit diagram showing a specific example of a detection circuit, FIG. 3 is a waveform diagram for explaining the operation of FIG. 2, and FIG. The figure is a waveform diagram for explaining the operation of the device. 1...Switching circuit, 21-2n...Detection circuit,
3...Counter, 4...Tecoder, 5...
...Logic differential circuit, 6...OR gate. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure, Qr.

Claims (1)

[Claims] An electronic switching circuit that includes a counter and a decoder and sequentially switches the input signal every time a clock pulse is applied to the counter is provided, and the output pulse of the decoder is delayed and differentiated, and the input signal is supplied to the input terminal. and the output signal of the switch to be switched according to the output signal, and the output of the logical product is added to the clock input terminal of the counter, so that when no input is supplied to the input terminal, A switching pulse generation circuit that advances the pulse so as to skip over its input terminal.