JPS6023384B2 - Internal memory control method in array processor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to internal memory control schemes in array processors.

FIG. 1 shows a part of the array processor, in which 1 is the main memory, 2 is the memory controller, 3 is the data register, 4 is the vector register, 5 is the buffer memory, and 6 is the access memory. The control section is shown.

The data register 3 is used as a general-purpose register or to store a descriptor, and the vector register 4 is used when executing a V-type instruction, and is a specific area of the main memory 1. A copy of the information shall be retained. The buffer memory 5 is used when performing scalar operations, and has the same function as a buffer memory in a normal central processing unit. Data from the access control unit 6 is transferred to a pipeline arithmetic unit (not shown), and a calculation result from the pipeline arithmetic unit is sent to the memory control device 2. For array processors, 3
An operand method is adopted, and a vector operation such as A←B*C can be performed.

The A, B, and C operands are vectors with multiple elements. A feature of array processors is that they can perform vector operations such as those described above at high speed. When increasing the speed of the array processor, the problem is how to access the internal memory IJ' such as the data register 3, vector register 4, and buffer memory 5 at high speed. be. FIG. 2 establishes a conventional internal memory control method. 1 shows internal memories such as vector registers, data registers, and buffer memory.

As shown in FIG. 2, in the prior art, consecutive addresses are allocated to a single memory device. For this reason, A←B*
When performing a vector operation called C, the discussion of the B operand, the discussion of the C operand, and the writing of the A operand are as follows:
They cannot be done at the same time.

SUMMARY OF THE INVENTION The present invention is intended to solve the above-mentioned problems, and it is an object of the present invention to provide an internal memory control method for an array processor that enables high-speed access processing to the internal memory of an array processor.

Therefore, the internal memory control method in the array processor of the present invention includes a main memory, a pipeline operation section, and an internal memory provided between the main memory and the pipeline operation section, and allows multiple elements to be controlled. In the array processor that processes the operations, the internal memory is divided into a plurality of independently accessible memory banks, and the plurality of operands required by the pipeline operation section are divided into corresponding plurality of operands. A bus is connected to each memory bank, so that a plurality of operands can be simultaneously written from or to different memory banks. Hereinafter, the present invention will be explained with reference to the drawings. FIG. 3 shows the main part of one embodiment of the present invention.
1-0 none, 11-3 are memory banks, 12 is a B operand bus, 13 is a C operand bus, 14 is an instruction bus, and 15 is an A operand bus.

Four memory banks 11-0 to 11-3 constitute one internal memory IJ device.

Memory banks 11-0 to 11-3 are assigned addresses as shown. Note that data access to each memory bank is performed in units of two words. It is now possible to read B operand and C operand data from the internal memory device simultaneously. Further, in the case of the one shown in FIG. 3, it is possible to simultaneously perform discussion/writing of three operands and programming of an instruction. As is clear from the above description, according to the present invention, writing data to the internal memory of the array processor or issuing data or instructions from the internal memory can be processed at high speed. It is possible to significantly improve the processing power of the entire processor.

[Brief explanation of the drawing]

Figure 1 is a diagram showing an overview of the array processor, Figure 2 is a diagram showing the internal memory configuration of the array processor, and Figure 3 is a diagram showing the configuration of the internal memory of the array processor.
The figure is a diagram showing the configuration of an internal memory used in the present invention. 1...Main memory, 2...Memo IJ control device, 3...Data register, 4...Vector
Register, 5... ~ buffer memory, 6... access control section, 11-0 to 11-3... memory bank, 12...B operand bus, 13...C
Operand bus, 14... Instruction bus, 15.
...A operand /ゞ. Nah bad ending Z bad ship

Claims (1)

[Claims] 1. An array that processes operations between multiple elements, including a main memory, a pipeline operation section, and an internal memory provided between the main memory and the pipeline operation section.
In the processor, the internal memory is divided into a plurality of independently accessible memory banks, and a plurality of operand buses are connected to each memory bank corresponding to the plurality of operands required by the pipeline operation section. 1. An internal memory control method characterized in that a plurality of operands can be simultaneously read from or written to different memory banks simultaneously.