JPS60236338A - data transmission equipment - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention provides a plurality of stations connected by a common transmission path each including a buffer memory for storing input/output signals, and a plurality of stations connected to each other by a common transmission path each having a buffer memory for storing an input/output signal. The present invention relates to a data transmission device that transmits and receives signals through a memory.

[Prior art]

Conventional devices of this type include the one described in Japanese Patent Application No. 1982-204G+1 and the one shown in the second factor. ・Figure 90 2 is a block factor showing the configuration of a conventional device of this type.
In particular, it concerns one station that cyclically transmits the take of a process control device or the like. Second
In Figure 2, the station converts the serial signal input via the transmission line (2) into a parallel signal, while
A signal converter (1) that converts the parallel signal of station ff1lB into a serial signal and sends it to the transmission line (2), a control circuit (8) that controls the operation inside the station, and temporarily stores input/output No. 1g. Consists of a buffer memory (4) and a switching circuit (6) that performs signal collection 2 and distribution for 10 input/output Mt1611 to (6n).
There is τ.

In the configuration shown in FIG. 2, process input/output devices (611 to
(According to the input signals of 6ns1, etc., the signals are sequentially read out via the switching circuit (5) and sequentially written into the corresponding locations of the buffer memory (4) according to the commands of the control (b) path (8). Next, the contents of this buffer memory (4) are sequentially read out in V% according to the commands of the control circuit (8), and converted into serial signals by the converter (1) for each number. The operation of transmitting the signal to the transmission path (2) is performed cyclically.

In other words, the input signal rsn from input/output i [f6]J~(6n) is
, AT reaches the opponent's Stergeon (not shown).

On the other hand, the other party's station (not shown) sends fL
'fc transmission line (2) serial signal, signal converter (1)
) is converted into a parallel signal, written to the buffer memory (4), and then output to the input/output devices U to (6n) via the switching circuit (5), which is the opposite of the input operation described above. It is performed cyclically with the flow of directional signals.

Since the conventional data transmission H111 has the above five FCils, the input/output signals were simply transmitted cyclically. Therefore, if the period of cyclic transmission is lengthened as the information room increases, and the transmission speed is substantially reduced by that amount, the number of points will increase.
c.

[Summary of the invention]

The purpose of the present invention is to eliminate the above-mentioned drawbacks.N stations connected by a common transmission path are each provided with a buffer memory for storing input/output signals, and the transmission path is connected via this buffer memory. In the device that transmits and receives signals, each station is connected to the mismatch horizontal l11:1 circuit', which compares the input/output signals with the contents stored in the expansion memory T/c f' and outputs all significant signals when there is a mismatch between the two signals. In addition to this, the present invention proposes a data transmission device that can reduce the number of nuisances and significantly increase the effective transmission speed by transmitting and receiving signals only when the unmatched exit route outputs a significant signal. It is.

[Embodiments of the invention]

The following is an example of the present invention? FIG. 1, in which the same parts as in FIG. 2 are denoted by the same reference numerals, will be described.

In Fig. 1, the input signals from the input/output devices (611 to (6n)) which are taken in through the switching circuit (5) are compared with the contents of the corresponding part of the buffer memory (4). (8) is a discrepancy detection circuit that outputs a significant signal "1" when the two do not match; (8) is a discrepancy detection circuit (9) which stores the results of (7); n each extra.

The operation of the data transmission device configured as described above will be explained below.

First, the input/output device f! ! In the same manner as described above, the input signals of +61) to (6n) are firstly read out via the switching path (6) according to the command from the control circuit (8), and the corresponding input signals are stored in the buffer memory (4). At this time, at the same time as reading the input signal, the contents of the corresponding part of the buffer memory (4) that were stored - period ago are also read, and the two are compared by the mismatch detection circuit (7). . As a result, when the two match, a signal of "0" is stored, and when they do not match, a signal of "1" (number 16) is stored in each memory (in addition to 81 and 1").
L. The control circuit (8) σ writes the results of the matching and non-matching results to the corresponding portion WrlC of the memory (8), while writing the state value of the input signal to the corresponding portion of the buffer memory (4).

Next, the control circuit (8) sequentially reads out the contents of the Hapanpha memory (4) and sends them out to the transmission line (2) via the signal converter (1).
8) is sequentially referred to, and only when the content is "1", the corresponding content of the buffer memory (4) is sent to the transmission line (2), and if it is "0", the content of the corresponding buffer memory (4) is sent to the transmission line (2). 2) Avoid sending.

In other words, data transmission is performed only when there is a change in the input signal 1c, and data transmission is not performed when there is no change in the input signal 1c. ) and a station shore (not shown) that performs all signal transmission and reception.Also, by adopting a configuration similar to this, the transmission time for a large number of signals can be significantly shortened, and the apparent transmission speed can be significantly increased accordingly.

1. In carrying out the above-described operations, it goes without saying that reading and writing to and from the buffer memory (4) must be performed in synchronization to avoid malfunctions.

By the way, in the above embodiment, the case where the serial signal of the process input/output device is sent to others as a single tone serial signal has been explained, but it is also possible for the stations that exchange signals with each other to send out the signal only when there is a change in both stations. In this case, it can be applied not only to process control and monitoring but also to remote control transmission devices other than those described above, and furthermore, it can be applied not only to devices that transmit serial signals but also to devices that transmit all parallel signals. Similarly, the present invention can be applied to the entirety of the present invention.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, a mismatch Yokota circuit is provided to detect a mismatch between an input/output signal that is cyclically transmitted and an input/output signal written in the buffer memory n one cycle before. Since the configuration is configured such that signals are sent and received only when there is a mismatch, the apparent transmission speed is greatly increased, and especially when applied to a control system VC where there are relatively few changes such as process input/output, This provides the advantage of being able to monitor and control an extremely large number of process quantities using one set of transmission lines.

[Brief explanation of the drawing]

The first example is a block diagram showing the configuration of a simple embodiment of the present invention, and FIG. 2 is a block diagram showing the configuration of a conventional device. (1); Signal converter (2): Transmission line (8): Control circuit (4): Buffer memory (5): Switching circuit (6~(6n): Process input/output device (7): Discrepancy detection (Ro ) Path (8): Memory for discrepancy judgment, (1
0a) New station Note that the same reference numerals in the figures indicate the same or corresponding parts. Agent Masuo Oiwa Figure 1 1 ♀ O Figure 2 1 Ω Procedural amendment (voluntary)], Indication of case Japanese Patent Application No. 59-094908 2, Title of invention data transmission device 3, Person making the amendment 5, Correction target 6, contents of correction, Figure 1 and Figure 2 are corrected as shown in the attached sheets. 7. Catalog drawing of attached documents 1 copy, North Figure 1 0a ＼ Figure 2 0 (

Claims (1)

[Claims] In a data transmission device in which a plurality of stations connected by a common transmission path are each equipped with a buffer memory for storing an input/output signal t, and transmit and receive signals to and from the transmission path via the buffer memory, the station Each includes a mismatch detection circuit that compares the content stored in the buffer memory with the human output signal and outputs a significant signal when the two do not match, and only when the mismatch detection circuit outputs a significant signal. A data transmission device characterized in that it sends and receives an ID code.