JPS60237724A - Complementary MOS logic gate - Google Patents

Abstract

PURPOSE:To reduce the through current of an output gate and also reduce power consumption and power source noises without providing any extra gate in front of the output gate by applying an input pulse to gates of a PMOS and an NMOS transistors (TR) which constitute the output gate at the same time. CONSTITUTION:The gate VG8 of the P type MOSTRQ8 and the gate VG9 of the M type MOSTRQ9 of the complementary MOS logical gate are connected to an input VIN3 in common. Further, drains of the TRs Q8 and Q9 are connected to an output VOUT in common and the source of the TRQ9 is connected to a power source VSS. Further, the source of the TRQ8 is connected to the drain of an N type MOSTRQ7, whose source and gate are connected to a power source VDD in common. Then, the input pulse with a high or low level is impressed to the input VIN3 and then the time when the TRs Q8 and Q9 turn on at the same time is shortened to reduce the through current of the output gate and also reduce the power consumption and power source noises.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to complementary MO8 logic, and particularly to a circuit system suitable for reducing output amplitude.

[Background of the invention]

The gate of the complementary MO& (hereinafter abbreviated as CMσS) structure outputs a voltage approximately equal to the voltage level of the voltage source connected to the gate.

If you use a voltage source with the same value as the TTL gate, TTL
Since the output level is considerably higher than that of a gate, as gate speeds increase, transmission line crosstalk and
The noise is also larger compared to a TTL gate. Therefore, when using a fast CMO8-IC in a slow and inexpensive conventional TTL gate mounting system, it is necessary to reduce the logic amplitude or slow down the output rise/fall time. . As a way to slow down the rise/fall time, as shown in Figure 1, the input VIN
There is a method to generate a mirror effect by inserting a capacitor C1 in parallel with I and the output VOUTI, but this method is not suitable for high-density packaging because the chip area occupied by the capacitor becomes large. One way to reduce the logic amplitude is to reduce the power supply voltage supplied to the IC, but when used in combination with TTL, the number of power supply types increases, which is impractical, and it is necessary to use a voltage source inside the IC chip. Although it is possible to manufacture and supply the power supply, the chip area occupied by the power supply circuit and power supply pattern becomes large.

As shown in FIG. 3, another method for reducing the logic amplitude is to reduce the amount of noise in the enhancement type N-channel transistor Q3 (GA3) constituting the output inverter G2.
Output V after inverting input VIN2 with inverter Gl
IN2 is applied, human power VIN2 is directly applied to the input GA4 of the enhancement type N-channel transistor Q4, and when VIN2 is at the LσW level, the enhancement type N
The channel transistor Q4 is set to σFF, while the enhancement type Q3 is applied with a voltage level of VDD in VIN2, and the output inverter G2 has a voltage level of V+ as shown in FIG.
There is a method to extract the output waveform 1b that is lower by the voltage level of h, but in addition to requiring an inverter G1 for each output gate, the enhancement type N-channel transistor Qs to the enhancement type N-channel transistor Q4 is required for the delay of the CMOS inverter G1. This has the drawback that a through current flows from the power supply VDD to VSS through the power supply, resulting in increased power consumption and power supply noise.

[Purpose of the invention]

An object of the present invention is to provide an 0MO8 logic gate with a reduced number of elements, low power consumption, low power supply noise, and reduced output logic amplitude.

[Summary of the invention]

K is the biggest advantage of CMσS IC, which is to configure a low logic amplitude output circuit without sacrificing low power consumption and suppressing an increase in the number of gates. It is ideal not to provide gates that cause an increase in power consumption and power supply noise due to an increase in through current caused by a phase difference between the signals applied to the input of the output gate. Due to the fact that the output of a gate depends on the voltage level of the voltage source applied to it, if the output circuit is composed of one CMOS gate and the voltage level applied to it is lowered, the output will meet the purpose of the present invention. gate can be realized. As a method of lowering the voltage level of the voltage source, high-density packaging is possible by using a simple level shifting element between the output gate and the voltage source to which it is applied, and using it in common between the output gates. It is.

[Embodiments of the invention]

An embodiment of the present invention is shown in FIGS. 5 and 6 below.

This will be explained with reference to FIG.

FIG. 6 shows an embodiment of the present invention, in which an enhancement type (hereinafter referred to as enhancement type unless otherwise specified) P-channel MOS transistor rLJTP
The gate VG8 of the M(") Qk run, the gate VG8 of the N channel MOS transistor (hereinafter abbreviated as NMOS transistor) and VO2 of the N channel MOS transistor (hereinafter abbreviated as NMOS transistor) are commonly connected to the input V
The drain of the NMOS transistor Q9 (DR8 and PMO8) is connected to IN3, the drain of the transistor Q8 is connected in common and the output is connected to the output of the NMOS
The source 809 of transistor Q9 is connected to the power supply Vss K and the source S of PMσS transistor Q8.

8 is connected to the drain of NMOS transistor Q7, and N
MO8) Source S7 and gate vG7 of transistor Q7
are commonly connected to the power supply VDDK. When a high level is applied to input VIN3, NM''?5S transistor Q
9 is ON), PMσS transistor Q8 is OFF
Therefore, a low level with a very low VssKi is output to the output VOUT3, and when a low level is applied to the input VIN3, contrary to the above, only the PMσS transistor Q8 is turned on. 5N', and NMO8 from the output level of power supply VDD.
) Threshold hold voltage value of transistor Q7 v+h7
A voltage level lowered by the amount of Yon is output to the output Yon〒1.

FIG. 7 shows the output waveform 2 of the output VOUT2 of the CMOS inverter shown in FIG.
The output waveform 2a of a is shown. VO2 and VG81 of NMOS transistor Q9 and PMOS transistor Q8
Since C input is applied at the same time, PMO8) transistor Q
Since the time that PMO 8) and NMOS transistor Q9 are simultaneously ON is short, the NMOS
Since the through current flowing through the transistor Q7 is small, power consumption is low and noise generation from the power supplies VDD and vss is also small.

8 to 12 show other embodiments of the present invention.

In (at, (b) of Fig. 8, PMOS transistors QIO, G14 are used as level shift transistors, and in (a), (b) of Fig. 9, normal diode D1 and Schottky diode are used, respectively. D2 is used for level shifting, and the first
In FIGS. 0(a) and 0(b), level shifting NMO8) transistors Q21, G22 and G25. G
This is an example of changing the connection method of 26, and (Q and () in Figure 1O).
(to) bipolar transistor Q2 for level shifting
9. This is an example in which the connection method of Q30, G33, and G34 is changed. In Fig. 11, the output amplitude of the output VOUT12 of the CMO82 human-powered NOR gate G2 is lowered, and in Fig. 13, the connection method of the CMOS inverter G3,
An example is shown in which G4 and G5 share the NMO8) transistor Q42 for level shifting.

〔Effect of the invention〕

According to the present invention, PMO8/NM constituting the output gate
Since the input pulses are applied at the same time, the through current of the output gate is small, so it is possible to reduce power consumption and power supply noise. However, since the level shift element can also be shared between the output gates, the number of elements used can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a solution different from the solution of the present invention, FIG. 2 is an output waveform diagram showing the operation of FIG. 1, and FIG. 3 is a circuit diagram showing a conventional example similar to the present invention. Fig. 4 is an output waveform diagram showing the operation of Fig. 3, Fig. 5 is a circuit diagram of a normal CMOS inverter, Fig. 6 is a circuit diagram showing an embodiment of the present invention, Fig. 7 is a diagram of Fig. 5, Output waveform diagram showing the operation of FIG. 6,
8 to 12 are circuit diagrams showing other embodiments of the present invention. Q9. G7...NM core S transistor Q8...PM
OS transistor VIN3...input, VOUT3...output VDD
* vss...voltage source. yf11 items 'N12 Figure 3 Edict Figure 4 Figure 5 Page 6 7th leap grn Figure 4 Figure 1 OU (υL) (b) (C) (壬)N

Claims (1)

[Claims] 1. Connect the gates of an enhancement type N-channel MOS transistor and an enhancement type P-channel MOS transistor of different polarities to each other as an input, and
Connect the drains/comrades of the OS transistors as an output,
A complementary MOS inverter is constructed by separately connecting the sources of the MOS transistors of different polarities to two voltage sources having different voltage levels. An enhancement type N-channel MOS transistor for level shifting is inserted in series between the source of the MσS transistor at the pole, and the source and gate are commonly connected as one terminal, and the drain is the other terminal. A complementary MO8 logic gate characterized in that the voltage level of the voltage source is lowered and taken out as an output of the complementary MOS inverter.