JPS60240141A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To improve the withstanding voltage between polycrystalline silicon elements and the yield rate, by growing a CVD oxide film between the first and second polycrystalline silicon elements and the third polycrystalline silicon element. CONSTITUTION:A field oxide film 102 is selectively formed on a semiconductor substrate 101. Then a first oxide film 103 is formed. A nitride film 104 is grown. Then first polycrystalline silicon 105 is grown, and patterning is performed. The first polycrystalline silicon 105 is thermally oxidized, and a second oxide film 106 is formed. Thereafter the nitride film 104 is etched, and the first oxide film 103 is etched. Second polycrystalline silicon is grown, and patterning is performed. A gate oxide film 107 at an extra part is etched, and a third oxide film 108 is formed by thermal oxidation. A fourth oxide film 110 is grown. After heat treatment, a contact hole 111 is formed by photoetching. Third polycrystalline silicon 112 is formed and patterned. A PSG film 113 is formed, a contact hole is provided and an aluminum wiring layer 114 is formed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of manufacturing a semiconductor device for improving breakdown voltage between multilayer electrode interconnections.

[Prior art]

FIG. 1 is a top view of a conventional dynamic memory cell, where l is an active region, 2 is a first polycrystalline silicon layer,
8 is an eighth polycrystalline silicon layer, 4 is a second polycrystalline silicon layer, 5 and 6 are contact layers, and 7 is an aluminum wiring layer.

FIG. 2 is a cross-sectional view taken along line A-A' in FIG.
12 is a semiconductor substrate, 12 is a field oxide film, 18 is a nitride film, 14 is a first polycrystalline silicon layer, 15 is an insulating film, 16 is a semiconductor substrate;
is the second polycrystalline silicon layer.

17 is a P2O layer, and 18 is an aluminum wiring layer.

Conventionally, due to the difference in the first polycrystalline silicon, the insulating film between the first and eighth polycrystalline silicon becomes thinner in the part B, resulting in a drop in breakdown voltage or short circuit, resulting in a defective device. The purpose of the present invention is to overcome such drawbacks, improve the pressure -bearing pressure between multiple crystalline silicon, and provide a method for manufacturing a semiconductor device for high walks.

[Structure of the invention]

The present invention includes a step of selectively forming a thick oxide film on a semiconductor substrate, a step of forming a first insulating film on the oxide film, and a step of forming a first polycrystalline silicon film on the first insulating film. a step of forming and patterning a layer, a step of thermally oxidizing the first polycrystalline silicon layer, a step of forming and patterning a second polycrystalline silicon layer, and a step of forming and patterning the second polycrystalline silicon layer. The method is characterized by including a step of thermal oxidation, a step of growing a CVD oxide film, and a step of forming and patterning a third polycrystalline silicon layer.

〔Example〕

The present invention will be described in detail below with reference to the drawings.

3(a) to 3(g) show cross-sectional views for explaining the manufacturing method according to the embodiment of the present invention. First, FIG. 3(a)
After selectively forming a field oxide film 102 on a semiconductor substrate 101 using a conventional technique as shown in FIG.
05 is grown and patterned by photo-etching.

Next, the first polycrystalline silicon 105 is thermally oxidized to form a second oxide film 106. Thereafter, the nuclear nitride film 104 is etched with phosphoric acid, and the first oxide film is further etched with a hydrofluoric acid-based etching solution. 103 to form a thermal oxide film 107 with a thickness of 300λ to 500X (FIG. 3(b)).

Subsequently, although not shown, second polycrystalline silicon is grown to a thickness of 4000^ to 6000λ and patterned.

After etching the excess portion of the gate oxide film 107 and thermally oxidizing it to form a third oxide film 108,
A thin drain portion 109 is formed by a method as shown in FIG.
c) 'e obtained 0 Then, as shown in FIG. 3(d), an A4 oxide film 110 is grown by 500X to 2000X by CVD method, and heat treated? to harden the fourth oxide film 110. This heat treatment may be omitted.

Next, as shown in FIG. 3(e), a contact hole 111 is formed by the 7-tooth etching method, and a third polycrystalline silicon y1 is formed.
Figure 3 (f>
After that, a PSG film 113 is formed in the same manner as in the conventional method, a contact hole (not shown) is made, and an aluminum wiring layer 114 is formed (FIG. 3(g)).

In this way, the drawback that the oxide film is not thin at the end of the first polycrystalline silicon due to etching, and the withstand voltage decreases or short circuit occurs between the edges of the first polycrystalline silicon and the third polycrystalline silicon is reduced. This problem can be solved by growing a CVD oxide film between the second polycrystalline silicon and the third polycrystalline silicon to a thickness of 500× to 2000×.

[4 Bright Effects] As explained above, according to the present invention, products that were defective due to a drop in breakdown voltage between polycrystalline silicon layers or due to 7 yotes become good products, so the yield rate of integrated circuits is significantly increased. It has the effect of improving

[Brief explanation of the drawing]

FIG. 1 is a top view of a dynamic memory cell according to a conventional example, FIG. 2 is a cross-sectional view taken along line A-A' in FIG. 1, and FIG. 3(a)
~(9) are cross-sectional views for explaining the manufacturing method according to the embodiments of the present invention.
...Contact hole no. turn 7..., aluminum wiring layer no. turn 11, 10
1... Semiconductor substrate 12.102... Field oxide film 13, 103.104... Insulating film 14.16, 105.112... Polycrystalline silicon layer 1
5, 106, 107, 108.110...Insulating film 17.113...PSG layer 18, 114...Aluminum wiring layer Patent applicant: NEC Corporation, -2B Fig. 2

Claims (1)

[Claims] A step of selectively forming a thick oxide film on a semiconductor substrate, a step of forming a first insulating film on the oxide film, and a step of forming a first insulating film on the semiconductor substrate. forming and patterning a crystalline silicon layer; thermally oxidizing the first polycrystalline silicon layer; forming and patterning a second polycrystalline silicon layer; and a second polycrystalline silicon layer. A method for manufacturing a semiconductor device, comprising the steps of thermally oxidizing G, growing an oxide film of G, and forming and patterning a third polycrystalline silicon layer.