JPS60242585A - semiconductor storage device - Google Patents

Abstract

PURPOSE:To increase the readout speed and optimize the sense margin by connecting a capacitive element to the common source line of a sense amplifier and setting a couple of data lines to a desired precharge level. CONSTITUTION:An MOS capacitor Cmp or Cmn utilizing the gate of an MOS FET is connected selectively to one of common source lines CSp and CSm of the sense amplifier SA equipped with MOSFETs Q5 and Q6 for controlling connections with a high and a low power source. This connection of the capacitor sets precharge levels of a couple of data lines D and D' to a desired value, and the precharge levels are not set to a half as high as a source voltage VCC, but adjusted to the optimum level according to data lines at sides L and H; and the rising of the data lines is speeded up, the readout speed is increased, and the sense margin is optimized.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to semiconductor memory technology, and relates to a technology that is effective when used, for example, in a data line precharging method in a dynamic semiconductor memory device.

[Background technology] Conventionally, dynamic RAM (random access
In general, latch-type sense amplifiers (memory) are used in
A dummy cell that stores an intermediate charge between information "1" stored in the memory cell and #Ort is connected to a complementary data line (or bit line) connected to a pair of input/output terminals of a flip-flop. The data line pair is precharged to the power supply voltage Vcc in advance, and when a memory cell connected to one data line is selected, a dummy cell on the other paired data line is simultaneously selected. do. Thereafter, the potential difference generated between the complementary data lines is detected and amplified by a sense amplifier, and read data is output.

On the other hand, the present applicant omitted the dummy cell connected to the complementary data line, and instead provided a switch between the complementary data lines that was short-circuited and turned on by a precharge signal. Vcc/2 data line pair
proposed a method of precharging to the level (hereinafter referred to as half precharging method)
No. 1).

In this method, after a complementary data line pair is precharged to Vcc/2, a switch for shorting between data lines is turned off, and then a word line is turned on. Then, the potential of the data line connected to the memory cell selected by the word line slightly deviates from Vcc/2 in accordance with the storage information 110H or III11. On the other hand, the potential of the other data line paired with this data line remains at Vcc/2. Therefore, by activating the sense amplifiers connected to the data line pair with an appropriate timing signal, the potential difference between the complementary data lines is amplified. Thereafter, desired data is read by turning on the column switch on the complementary data line corresponding to the Y-system address signal and connecting the complementary data line to the main amplifier via the common data line.

According to the above half precharge method, the precharge level of the complementary data line pair is half that of the conventional method.
will be lowered to Therefore, the current consumption associated with precharging the data line is reduced, and the precharging time is also shortened.

By the way, in the invention of the prior application, the precharge level of the complementary data line is set to Vcc/2. However, due to the symmetry of the elements and wiring connected to each pair of complementary data lines, the parasitic capacitance of each data line becomes equal. /2 is precharged. In other words, according to the prior invention, if the parasitic capacitances connected to each data line become unbalanced due to the layout of circuit elements and wiring, a precharge level of Vcc/2 level cannot be guaranteed. do not have.

However, even when the half precharge method is used, there is no established theory as to whether the most appropriate level for data line precharge is Vcc/2. In other words, if the precharge level is lower than Vcc/2,
The drawing of the data line on the row side is delayed, but the MO3FET is a switch for selecting memory cells in which information charges are accumulated.
Since the transition to the on state becomes faster, the rise of the high-side data line becomes faster. On the other hand, if the precharge level is higher than Vcc/2, the transition to the on state of the MOSFET of the memory cell in which high information is stored will be delayed, making it difficult to output high information, but the low data line This has the advantage that charge extraction becomes faster and the speed at which the level difference between the data lines increases when the sense amplifier is activated also becomes faster.

Therefore, the precharge level of the complementary data line is set to Vcc/
If the precharge level can be arbitrarily adjusted using an appropriate means instead of 2, it is possible to achieve a desired precharge level according to the memory design standards, design philosophy, circuit format, etc., and increase the read speed and sense margin. This is very convenient as it allows for optimization.

[Object of the Invention] An object of the present invention is to provide a technology that enables faster read speed and optimization of sense margin in a dynamic RAM to which a data line half precharge method is applied. be.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Summary of the Invention] Representative inventions disclosed in this application will be summarized as follows.

In other words, if the parasitic capacitance on each data line is unbalanced, the precharge level will deviate from Vcc/2, and the parasitic capacitance on each data line may be parasitic on the common source line of the MOSFETs forming the sense amplifier. By focusing on the fact that the common source line includes a capacitance that uses MO8 capacitance, etc., the capacitance connected to the complementary data line is unbalanced by a predetermined amount, and This achieves the above object of being able to set the precharge level of the data line to any value between power supply voltages Vcc and Vss.

Embodiment FIG. 1 is a circuit diagram showing a schematic configuration of an embodiment in which the present invention is applied to a dynamic RAM.

The memory array M-ARY includes known 1MO8 type memory cells arranged in a matrix. However, the drawing shows the inside of the memory array.

Only one pair of memory rows is representatively shown, with complementary data lines placed parallel to this memory row.

D and a word line Ws arranged in a direction perpendicular to this
r W2 y ・=・Wn, switch MO8F, E
TQz I F Q, 21' = - Each input/output node of the memory cell configured with Qln and MO8 capacitor is 1. As shown in the figure, the memory arrays are distributed and combined with a predetermined regularity to form a so-called two-intersection type (or folded bit line type) memory array.

The word lines W1 to Wn connected to the gate terminals of the switches MO8FETQI1 to Q1n are MOSFETQ
Address signal Axi formed from a polysilicon layer integrated with the gate electrode of 11-Ql n and supplied from the outside.
One of them is set to the selection level by the row address decoder circuit R-DCR that decodes the row address decoder circuit R-DCR.

A precharge signal φp is provided between the complementary data line and D.
A precharge switch MO5FETQp whose on/off is controlled by c and a sense amplifier SA made up of a CMOS latch circuit are provided. The switch MOSFET lp is formed into a p-channel type, although it is not particularly limited. As shown in the figure, the sense amplifier SA includes P-channel type MO8FETQ1. Q3, and n-channel MoS, FETQ2. ' Q4, and its pair of input/output nodes are coupled to the complementary data line D.

In addition, the complementary data line D is a column switch Qy
1. Common data line CD via Qy2.

Connected to CD. Column switch Q y 11Q
'12 is an n-channel type MO, although it is not particularly limited.
It is constituted by an SFET and is controlled to be turned on or off by an output signal of a column address decoder C-DCR that decodes a Y-system address signal Ayi supplied from the outside.

The above sense amplifier SA and column switch Qy1r
Qyz is also provided on other complementary data lines (not shown),
A sense amplifier row and a column switch row are arranged on one side of the memory array M-ARY.

MOSFETQI, which constitutes a sense amplifier SA consisting of a CMOS latch circuit provided for each complementary data line;
Q3 and Q2. The respective source terminals of Q4 are connected to each other by common source lines CSp and C8n. The latch circuit also includes a common source line C8.
p-channel type MOS FET connected to P
Power supply voltage Vcc is supplied through Q5, and
n-channel type MO8 connected to common source line CSn
The ground voltage Vss of the circuit is supplied through FETQ6.

Timing signals 11 and φ, which are substantially complementary to each other, are applied to the gates of the MO8FETs Q5 and C6, and the sense amplifier SA is activated by the timing signals φp and φN.

In this embodiment, the common source lines C5p and C
An MO5O5 capacitor p or Cmn using the gate electrode of the MO'5FET is provided near the MO'5FET, and an MO8 capacitor mp or Cmn is selectively connected to either the common source line C8p or CSn. Being connected.

In the above embodiment, the precharge signal φpc changes from a low level to a high level in synchronization with the fall of a control signal such as an externally supplied RAS signal (row address strobe signal). changed to. Then, MO8FETQP for precharging is turned off, and complementary data AID and D are separated. By this time, the complementary data lines, D, are at the same level (Vcc
and Vss), and when one of the word lines W is set to the selection level after the precharge signal φpc rises, one or the other word line W is set to the selection level depending on the information charge of the selected memory cell. The level of the data line changes. Thereafter, the timing signal φ rises, and then the timing signal EV falls, so that the power supply voltages Vcc and Vss are supplied to the sense amplifier SA via the common source lines csp and csn. Then, the sense amplifier SA is activated, the level of the complementary data line D rapidly increases, and the read data (level difference between the data lines) is amplified. Then, the pair of column switches Qy1y Qyz are turned on by the output signal from the column address gater C-DCR, and the selected complementary data line pair D is connected to the common data lines CD and CD, and the main amplifier MA The read data is further amplified and output to the outside via an output sofa circuit (not shown).

When the RAS signal rises to high level after data reading, the timing signal φP is changed to high level and φN is changed to low level in synchronization with this. Therefore, sense amplifier SA is disconnected from power supply voltages Vcc and Vss, and common source lines C8p, C, Sn and complementary data lines D are placed in a floating state.

After that, the precharge signal φpc is changed from high level to low level, and the M○5FETQP for precharging is
is turned on. As a result, the levels of the data lines '5, which had been determined to be Vcc level on one side and Vss level (0■) on the other, are brought to the same potential by the movement of charges.

At this time, part of the charge on the data line with higher potential is
Sense amplifier SA n-channel type M○S 'F E
A part of the charge flowing into the common source line C8n on the Vss side through T Q 2 or C4, and on the common source line C8P on the Vcc side is transferred to the p-channel type M of the sense amplifier SA.
It flows into the data line through OS FET Q 1 or C3.

Therefore, in this embodiment, the common source line C3 on the Vcc side
If the MO8 capacitor Cmp is connected to p, the capacitance (including parasitic capacitance) connected to the common source lines C3p and C8n with MO3FETQs and C6 turned off after data reading will be connected to the common source line C8P. becomes larger than C8n. Therefore, MO8FETQp for precharging
When turned on, the amount of charge flowing from the common source line C8p to the data line D side is greater than the amount of charge flowing from the data line to the common source line C3n.

As a result, the common source line C8P has an MO8 capacitance m p
If connected, the data line is connected.

5 is the power supply voltage ■ intermediate potential Vcc/2 between CC and vSS
is precharged to a slightly higher potential.

On the other hand, if the MO8 capacitor Cmn is connected to the common source line C8n on the Vss side, the MOS
The capacitance (including parasitic capacitance) connected to the common source lines C8p and C8n with FETQs and C6 turned off is larger for the common source line C8n than for C5P. Therefore, when the precharge MOSFET Qp is turned on, the data line and the common source line C8 are connected from the D side.
data line from the common source line C8p than the amount of charge flowing into n.

The amount of charge flowing to the D side is smaller. As a result, when the MO8 capacitor Cmn is connected to the common source line C8n, the data line D is precharged to a potential slightly lower than the potential Vcc/2, which is between the power supply voltages Vcc and Vss.

In other words, by connecting an appropriately sized MO8 capacitor to either the common source line C8p or C3n,
The data line, the precharge level of '5 is set to the power supply voltage Vc
It can be set to any potential between c and Vss.

Next, an example of the layout of the MO8 capacitor in the above embodiment will be explained using FIG. 3.

Note that the semiconductor memory device of the embodiment is manufactured, for example, by the following manufacturing method.

A semiconductor substrate made of single-crystal P-type silicon is prepared, and an N-type well region is formed on its surface.

Non-active regions on the main surface of the semiconductor substrate, ie, MOSFETs and MOS capacitors, are formed using selective oxidation technology.

A relatively thick field oxide film is formed in a region excluding a so-called active region where a semiconductor wiring region and the like are formed.

After removing an oxidation-resistant mask such as a silicon nitride film used in selective oxidation, a gate oxide film is formed on the surface of the active region by thermal oxidation.

A contact hole is formed in the gate oxide film by selective etching technology to enable direct contact between the source or drain region of the N-channel MO8FET to be formed later and the polysilicon layer, and then CVD is performed on the main surface of the semiconductor substrate. A polysilicon layer is formed by.

After making the polysilicon layer N-type by phosphorus treatment, the polysilicon layer is selectively etched.

As a result, a polysilicon layer to be used as a gate electrode and wiring remains on the semiconductor substrate.

The source and drain regions of the P-type channel MO8FET are formed by introducing P-type impurities such as boron into the surface of the N-type well region by ion implantation. Note that in this ion implantation, N-channel MO5
The area where the FET is to be formed must be covered by an ion implantation mask, such as a photoresist film. The formed source and drain regions are self-aligned with the polysilicon layer and field insulating film, since the polysilicon layer and field insulating film act as a kind of mask.

Thereafter, with the P-channel MO5FET forming portion covered with an ion implantation mask, an N-type impurity such as phosphorus is introduced into the surface of the semiconductor substrate by ion implantation to form the source and drain regions of the N-channel MO5FET. The source and train regions at this time are self-aligned with respect to the polysilicon layer and the field insulating film, similar to those of the P-channel MO3FET.

After appropriate annealing of the ion implantation region, an interlayer insulating film, such as a silicon oxide film, is deposited over the entire main surface of the semiconductor substrate.

After forming a contact hole in the interlayer insulating film, an aluminum layer is formed on the semiconductor substrate. Thereafter, the aluminum layer is selectively etched.

Thereafter, a final passivation film having a two-layer structure of a phosphosilicade glass film and a silicon nitride film is formed. The device is completed by removing the final passivation film from the previously formed bonding pad electrode layer.

In the drawings showing the layout described below, the pattern of the active region, ie the pattern of the area surrounded by the field insulating film, is shown by broken lines, and the pattern of the polysilicon layer is shown by dashed lines. Also, the pattern of the aluminum layer is shown by solid lines. A contact hole for coupling the polysilicon layer to the source and drain regions of the MOSFET is shown by a combination of an X mark and a chain double-dashed line. Further, contact holes provided in the glabella insulating film are shown by a combination of an X mark and a solid line.

FIG. 3 shows an n-channel type MO8FE constituting the sense amplifier SA connected at one end of the complementary data line D.
A plan view showing an example of the layout of TQ2, Q4, and the MO8 capacitor Cmn connected to the common source line C8n on the Vss side of the sense amplifier SA is shown.

In the same figure, what is indicated by la and lb are n-channel type MO8FETQ that constitutes the sense amplifier.
2 and Q4 source regions, and 2a,
2b shows the same <MO3FETQ2 and Q
This is an N-type diffusion region that becomes the drain region of No. 4. These N-type diffusion regions 1a, lb.

2a and 2b are formed on the main surface of a semiconductor substrate such as silicon. Then, between the N-type diffusion regions 1a and 2a and between lb and 2b, a MOS FE is provided.
Polysilicon layers 3a and 3b are formed to serve as gate electrodes of TQ2 and Q4. Each polysilicon layer 3a and 3b is connected to the other M through holes 4a and 4b, respectively.
The drain regions 2b and 2a of O8FE'r are contacted, thereby causing the drain voltage of one MOS FETQ2 (or Q4) to be the same as that of the other MOS FETQ2 (or Q4).
A sense amplifier circuit connection is made as shown in FIG. 1, which is applied to the gate of Q 4 (or Q2). Therefore, the channel portions of the MO8FETs Q2 and Q4 are formed at the locations shown by diagonal lines 5a and 5b in the figure.

In addition, these MO8 are provided in the source regions 1a and ib.
It is contacted via contact holes 7a and 7b to a common source line 6 formed on a region where FETs Q2 and Q4 are formed so as to cover them with an insulating film interposed therebetween. This common source line 6 is formed of an aluminum layer along the sense amplifier row. That is, below the common source line 6 (C5n) formed with a relatively wide width, the n-channel portions O, S F E constituting the sense amplifier are connected.
TQ2.

Q4 is installed. In addition, the above source area engineering a and 1
b is formed integrally with the source region of N-MO3 of the adjacent sense amplifier.

Further, next to and parallel to the common source line 6, a Vss line 8 also made of an aluminum layer is provided, and below this Vss line.

An electrode 9 made of a polysilicon layer is formed, and this electrode 9
An N-type diffusion region IO is formed on the main surface of the substrate below. The electrode 9 and the N-type diffusion region 10 are, for example, a polysilicon electrode (or a gate electrode of MO8FETQ2, Q4) constituting an MO8 capacitor in a memory cell, which will be described later, and an N-type diffusion layer (
Alternatively, they are formed simultaneously with the N-type diffusion regions 2a, 2b). An insulating film is formed between the electrode 9 and the N-type diffusion layer 10 and between the electrode 9 and the Vss line 8 thereon.

A contact hole 1 is provided in the N-type diffusion layer 10.
The common source line 6 is connected to the polysilicon electrode 9 through a through hole 12 . the result,
An MO8 capacitor between the polysilicon electrode 9 and the N-type diffusion layer 10 is connected between the common source line 6 (C8n) and the power supply voltage Vss, and a circuit as shown in FIG. 2 is realized. Ru.

Furthermore, a plurality of polysilicon electrodes 9 and N-type diffusion layers 10 below the Vss line 8 are formed at appropriate pitches (every other pair of complementary data lines) along the direction in which the Vss line 8 is arranged. There is. Therefore, by appropriately setting the locations where contact holes 11 (or through holes 12) are formed for these polysilicon electrodes 9 (or N-type diffusion layer 10), the number of MO3 capacitors connected to common source line 6 can be increased. can be decided arbitrarily. As a result, the size of the MO8 capacitor connected to the common source line 6 can be arbitrarily set to realize a desired precharge level (<Vcc/2).

On the other hand, if you want to set the precharge level higher than Vcc/2 by connecting an MO8 capacitor to the common source line C8P on the Vce side of the sense amplifier SA in FIG. The sense amplifier p-channel type MO8FETQ1. Q
A diffusion region is formed on the main surface of the substrate on the side of s. Further, a polysilicon electrode 9 is formed above this diffusion region, and furthermore, a Vcc line is formed in parallel to the common source line C8p made of an aluminum layer, and a Vcc line is formed in an appropriate diffusion region.
Touch the c line. This causes M to be applied to the common source line C8p on the Vce side of the C, MoS type sense amplifier
Connect the O8 capacitor and set the precharge level of the data line to Vcc/2. It is also possible to increase the temperature of nigiri.

However, in the above case, the P-channel type MO8FETQ1. Contact of the other MOS gate electrode to the source and drain regions of Qs must be made through aluminum if N-type impurities are implanted into the polysilicon layer to lower the resistance of the polysilicon gate electrode. .

FIG. 4 shows an example of the layout of memory cells and data lines. That is, on the main surface of the semiconductor substrate, a switch MO8FET (Ql
-Qn), the N-type diffusion layer 13 that becomes the drain region of the MOSFET, the source region of the MOSFET, and the MOSFET for storing information charge.
An N-type diffusion layer 14 that constitutes one electrode of the three capacitors is formed.

As shown in the figure, the N-type diffusion layers 13 and 14 are formed symmetrically with respect to each other in adjacent memory cells, and are arranged with a predetermined regularity.

On the N-type diffusion layer 14, a first polysilicon layer 15, which becomes the other electrode of the MO8 capacitor, is placed via an insulating film.
The diffusion layer 1 is formed so as to continuously cover the upper part of the substrate.
A rectangular window 15a is formed at the location where 3 is formed. A second polysilicon layer 16, which will become the gate electrode and word line of the switches MO8FE (Q 1 -Q n ), is formed via a rim film so as to intersect with this window 15a.

After forming this polysilicon layer 16, the window 15a is
By implanting N-type impurity ions onto the main surface of the substrate, the source and drain regions of the MO8FET are formed in a self-aligned manner. As a result, the switch MO8FET is installed at the location shown by diagonal lines 17 in the same figure.
Channel portions (Q11 to Q1n) are formed.

Further, a data line 18 made of an aluminum layer is formed along a direction perpendicular to the polysilicon layer (word line) 16 and intersects with the window 15a. This data line 18 is in contact with a common drain region (N-type diffusion layer 13) of the switch MO8FETs constituting the memory cells of each row through a contact hole 19.

One end of the data line 18 made of an aluminum layer is
Polysilicon layer 3a in the sense amplifier shown in FIG. 3 through through hole 20.

3b, a circuit configuration is realized in which a latch type sense amplifier SA is connected to each pair of complementary data lines D, as shown in FIG.

Note that in the above embodiment, the common source line cSp or CS
MOS capacitor Cmp or Cmn connected to n is newly set to Vss in parallel with the sense amplifier row in the memory array
Although a line is provided and the capacitance is formed under the line, it is also possible to provide a MO8O8 capacitor Cmn outside the memory array. In addition, in the above embodiment, a RAM having a CMOS latch circuit type sense amplifier
Although we have explained the case where it is applied to a RAM that has a sense amplifier consisting only of n-channel MOSFETs,
It can also be applied to

[Effect] Prior to selection of a pair of data lines, the switch MO8FET provided between the data line pair is turned on to precharge the data line pair to a potential between power supply voltages Vcc and Vss. In a precharge type dynamic RAM, by adding a capacitive element using an MO8 capacitor or the like to the common source line of the latch type sense amplifier connected between each data line pair, the capacitor connected to the complementary data line can be increased. are unbalanced by a predetermined amount in advance, so when the sense amplifier is activated, the amount of charge flowing from the common source line to one data line and the other'
Due to the effect that the amount of charge flowing from one data line to the common source line differs by a certain amount, the precharge level of the data line can be set to any value between the power supply voltages Vcc and Vss. Become. As a result, the sense margin can be optimized and the read speed can be increased.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, in the above embodiment,
MO8 capacitor is actively connected to the common source line of the sense amplifier in order to set the precharge level of the data line, but the capacitor (including parasitic capacitance) connected to the common source line is on the Vce side and Vss side. This may result in an imbalance. Therefore, instead of connecting MO8 capacitor,
It is also possible to adjust the precharge level by changing the size of the parasitic capacitance connected to each common source line, such as by changing the thickness of the common source lines C8p and C8n.

[Field of Application] In the above explanation, the invention made by the present inventor was mainly applied to a two-intersection type dynamic RAM, which is the field of application that formed the background of the invention.
It can be used in dynamic RAMs of the one-crossing point type (open bit line type) and all other semiconductor memory devices that have complementary data lines and are designed to be precharged at the time of selection.

[Brief explanation of the drawing]

Fig. 1 is a schematic circuit configuration diagram showing an embodiment of the main part when the present invention is applied to a dynamic RAM, Fig. 2 is a timing chart thereof, and Fig. 3 shows the main part of the sense amplifier and common components. FIG. 4 is an explanatory plan view showing an example of a layout configuration of an MO5 capacitor connected to a source line. FIG. 4 is an explanatory plan view showing an example of a layout configuration in a RAM memory array to which the present invention is applied. M-ARY...Memory array, D,'5...Complementary data line, W1~Wn...Word line, Ql,~Q
1n...Switch MO3FET, Qp...Precharge switch MO8FET, R-DCR...
Row address decoder, C-DCR...Column address decoder, SA...Sense amplifier, MA...
・Main amplifier, CD, CD・°°°Common data line,
Q y i r Q y 2...Column switch,
C8p, C8n... common source line, Cmp, Cmn
-MO8 capacity, la, lb, 2a. 2b...N-type diffusion region, 3a, 3b...polysilicon layer, 4a, 4b...through hole, 5a. 5b...Channel section, 6...Common source line,
7a, 7b, 11...contact hole, 8...
・Vss line, 9... Polysilicon electrode, 10.
...N type diffusion layer, 12...Through hole, 13゜14...N type diffusion layer, 15...Polysilicon layer, 15a...Window, 16...Poly Silicon layer (word line), 17...channel section, 18...data line, 19...contact hole, 20...
Through hole.

Claims (1)

[Claims] 1. A plurality of memory cells are arranged in a matrix, and a data line is arranged corresponding to each memory column, and the input of the memory cells of that column is connected to this data line. a memory array to which an output node is connected; the data lines are connected in pairs to a pair of input/output terminals of a sense amplifier constituted by one latch circuit; In a semiconductor memory device in which a switch element capable of short-circuiting the data line pair is provided between the data line pairs, a capacitive element of an appropriate size is provided on the common source line of the sense amplifier, and a capacitor element of an appropriate size is provided between the data line pairs. 1. A semiconductor memory device characterized in that when a switch element is turned on to precharge the data lines, the potential of each pair of data lines is set to a desired precharge level. 2. In the case where the sense amplifier is configured with 0MO8 U-Sochi plane circuits, a common source line that connects the sources of a pair of P-channel type MO8FETs constituting this CMOS latch circuit to a common charge-up MO8FET, or By connecting the capacitive element to either one of the common source lines that connect the sources of the pair of n-channel MO8FETs constituting the CMOS latch circuit to a common MO8FET for charge extraction, 2. The semiconductor memory device according to claim 1, wherein the charge level is set to a desired value. 3. The capacitive element includes a diffusion layer formed on the semiconductor main surface below the aluminum layer constituting the common source line, and a polysilicon layer formed on the diffusion layer with an insulating film interposed therebetween. 3. The semiconductor memory device according to claim 2, wherein the semiconductor memory device is a MoS capacitor formed between the semiconductor memory devices.