JPS60242595A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To eliminate the need to provide an exclusive area for a ROM in a gate array by constituting the ROM by using transistors (Tr) arrayed laterally in a column in the gate array as information storage and address selection TRs in the same column. CONSTITUTION:Storage blocks 21a-21d, a MOSTr6e, and a logical inversion type buffer 9 are coupled laterally to constitute a ROM main body 22. For example, if a source voltage value appears at a row decoding output 4a and a column decoding output 14 as the result of the decoding of address inputs 2 and 3, and 11 and 12, logic 1 is outputted to an information output terminal 10. Then, when the source voltage value is outputted to a row decoding output 4b and a column output 14a, the potential of a bit line 5f does not varies and logic 0 appears at a terminal 10 because the drain or source of a MOSTr15j is not connected to the source or drain of a MOSTr20a. Thus, the ROM is constituted to eliminate the need to provide the exclusive area for the ROM in the gate array and also forms the ROM efficiently in the gate array.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a semiconductor integrated circuit device, particularly a MOS gate array LSI (hereinafter referred to as a gate array), and a read-only memory circuit (hereinafter referred to as a ROM) of an arbitrary size therein. The present invention relates to a semiconductor integrated circuit device that can have a built-in device.

[Prior art]

Generally, a ROM using MOS transistors has a circuit configuration shown in FIG. Here, a ROM having a structure of 16 words x 1 bit will be explained.

In the figure, 1 is a row decoder, upper (or lower) addresses 2 and 3 are connected to the input, and row decoder output 4
a to 4d are bit lines 5a, 5b, 5c, through which information is transmitted;
5d so as not to be connected to each other, and are arranged so as to form a mesh shape. The bit lines 5a to 5d include MOS) transistors a to 6d, each source (or drain), and a MOS transistor to select a required bit line from bit lines 5a to 5d, each drain (or source) of each transistor a to 7d. ) are connected to each other.

The sources (or drains) of bit line selection MO3) transistors a to 7d are all connected to the input of a logic inversion type buffer 9, and the output of the buffer 9 is connected to the information output terminal 1.
Connected to 0. Each gate of the bit line selection MO3I-transistor a to 7d is connected to the column decoder 1 whose lower (or upper) address 11°12 is connected to its input.
It is connected to the decode outputs 14a to 14d of No. 3.

At the intersections of the row decode outputs 4a to 4d and the bit lines 5a to 5d, which are arranged in a grid pattern, there are MOSs storing information.
) transistors 15a to 15h are arranged, and each of these gates connects each source (
The drains (or drains) are connected to the bit lines 5a to 5d, and each drain (or source) is connected to ground.

The number and intersections of the information storage MOS transistors to which they are connected vary depending on the type of information corresponding to the address required by the ROM. However, M that remembers information
OS) For transistors, the gate is always the row decode output,
The drain (or source) is connected to the bit line, and the source (or drain) is connected to ground.

Next, the operation will be explained. In FIG. 1, the address from which information is to be read is added to address input 2.3°11.12. The address is decoded by the row decoder 1 and column decoder 13, and the selected output outputs the power supply voltage value.

Note that the other decoder outputs are approximately at ground potential.

Here, as a result of decoding the address input 2°3 by the row decoder 1 and the address input 11°12 by the column decoder 13, a row decode output 4b and a column decode output 1 are obtained.
Assume that the power supply voltage value is output to 4b. When the row decode output 4b outputs the power supply voltage value, the MOS transistor 15d becomes conductive, and the bit line 5b, which had been previously charged to the power supply voltage value by the MOS transistor b, becomes conductive.
lower the potential to near ground potential. The potential of the bit line 5b is propagated to the common bit line 5e through the MO3I-Ranji stuff b which is in a conductive state as the column decode output 14b outputs the power supply voltage value. The logic of the voltage propagated to the common bit line 5e is inverted by the logic inversion buffer 9, that is, the power supply voltage value is output, and the logic "1" (power supply voltage value) is output to the information output terminal 10. The above is a case where the information of the selected address in the ROM is "1", but if the information of the selected address is "0", the following operation is performed.

Now enter the address to read the information 2゜3.1
In addition to 1.12, suppose that as a result of decoding by the row decoder 1 and column decoder 13, a power supply voltage value is output to the row decode output 4b and the column decode output 14C. By the row decode output 4b outputting the power supply voltage value, the MO
Although the S) transistor 15d is conductive, the source (or drain) of the MOS transistor 15d is not connected to the pinto line 5C, so the potential of the bit line 5C, which was previously charged by the MOS transistor 6c, does not change. As a result, the bit line 5C potential is propagated to the common focus line 5e by the MOS transistor 7C, which is rendered conductive by the power supply voltage value outputted to the column decode output 14c, and the logic of the voltage is inverted by the logic inversion type buffer 9.
In other words, it outputs a value close to the ground voltage, and outputs the logic "θ" (the ground voltage value) to the information output terminal 10.

As described above, the row decoder 1 decodes outputs 4a to 4.
Whether or not to place a MOS transistor at a position where the "1" output selected from d intersects with the common bit line 5e and the bit lines 5a to 5d which are electrically connected by the MOS transistors 7a to 7d selected by the column decoder 13. The type of information is determined by

Conventional semiconductor integrated circuit devices are configured as described above, so when trying to incorporate a ROM in a gate array, an RO is placed on a horizontally structured transistor row in the gate array.
As shown in FIG. 2, there is a ROM dedicated area 19 in addition to the logic circuit area 18 on the gate array chip 1G.
will have to be established. Furthermore, the size of the ROM to be incorporated is limited by the size of the ROM dedicated area, and there is no degree of freedom.
If it is smaller than the dedicated area, there are drawbacks such as poor usage efficiency of the ROM dedicated area. Note that 17 in Figure 2 is I
10 buffers.

[Summary of the invention]

This invention was made in order to eliminate the drawbacks of the conventional ones as described above, and it is a ROM that uses transistors arranged on the same line as information storage transistors and address selection transistors in the same column (or row). By configuring this, ROM can be mixed with logic circuits without creating a ROM-dedicated area, ROM of any size can be built into the gate array, and even MOS (in LSI) can be used.
DESCRIPTION OF THE PREFERRED EMBODIMENTS An object of the present invention is to provide a semiconductor integrated circuit device capable of improving the efficiency of use of transistors. [Embodiment of the Invention] An embodiment of the present invention will be described below with reference to the drawings.

FIG. 3 shows a semiconductor integrated circuit device according to an embodiment of the present invention. In the figure, the same reference numerals as in FIG. 2 indicate the same parts. In the device of this embodiment, the logic circuit area 18 contains a ROM configured by using transistors arranged horizontally in the same column (row) as information storage and address selection transistors, as well as logic elements. A dedicated ROM area 19 as shown in FIG. 2 is not required.

Further, FIG. 4 shows the RO provided in the logic circuit area of FIG.
Indicates M. However, the bit configuration of this ROM is the same <16xl bit configuration as in FIG. 1.

In the figure, 15i to 151, 20a, and 6e are MOS transistors arranged horizontally in a row in the gate array, and the sources (or drains) of the MOS transistors 15i to 151 that store information are connected to the bit line 5f. , each gate is connected to the decode outputs 4a to 4d of the row decoder 1 which receives the upper (or lower) address 2.3, and the MO
S) Each drain (or source) of the transistors 15i and 15 is a MOSFET 20 for selecting the address to be read.
connected to the source (or drain) of a, MOSFE
The drain (or source) of T20a is connected to ground, and the gate is connected to the decode output 14a of the column decoder 13, which receives the lower (or upper) addresses 11 and 12, respectively. The source (or drain) of the transistor (MOS) transistor e is connected to the bit line 5f, and the gate and drain (or source) are connected to the power supply terminal 8. bit line 5f
is connected to the input of the logic inversion type buffer 9, and the output of the logic inversion type buffer 9 is connected to the information output terminal 10. MOS) transistors 151 to 1 of memory block 21a
51.20a has the above structure, but the other memory blocks 21b to 21d also have a similar MOS) transistor connection structure.

Each of the memory blocks 21b to 21d has a row decode output 4a.
.about.4d and the bit line 5f in the same way as the memory block 21a. Further, just as the column decode output 14a is connected to the gate of the MOS transistor 20a in the memory block 21a, the column decode outputs 14b to 14d are connected to the gates of the MOS transistors in the memory blocks 21b to 21d, respectively. . Then, the above memory blocks 21a to 21d, MO3I-transistoro e, and logic inversion type buffer 9 are horizontally connected to form the ROM main body 2.
2 are configured.

Next, the operation will be explained. It is assumed that necessary information is set in advance for all addresses in the ROM.

Now, in FIG. 4, as a result of decoding the upper (or lower) address inputs 2 and 3 by the row decoder 1 and the lower (or upper) address inputs 11 and 12 by the column decoder 13, the row decode output 4a and the column decode output 14
Assume that the power supply voltage value is output to a. Row decode output 4
As a and column decode output 14a output the power supply voltage value, MOS) transistors 15i and 20a become conductive, and the potential of bit line 5f, which had been previously charged to the power supply voltage value by MOS) transistor e, is lowered to near the ground potential. . The logic of the voltage on the bit line 5f is inverted by the logic inversion buffer 9, that is, the power supply voltage value is output, and the logic "1" (power supply voltage value) is output to the information output terminal 10. The above is a case where the information of the selected address in the ROM is "1", but if the information of the selected address is "0", the following operation is performed.

Now enter the address to read the information 2゜3.1
In addition to 1.12, assume that as a result of decoding by the row decoder 1 and column decoder 13, a power supply voltage value is output to the row decode output 4b and the column decode output 14a. When the decode outputs 4b and 14a output the power supply voltage value, the MOS transistors 15j and 20a become conductive, but the M
OS) The drain (or source) of the transistor 15j is the source (or drain) of the MOS transistor 20a.
Since it is not connected to the bit line 5f (MOS), which is charged to the power supply voltage value by the range screen e, the potential of the bit line 5f does not change, and the logic of that potential is inverted by the logic inversion buffer 9, that is, it becomes a value close to the ground voltage. and outputs a logic "O" (above ground voltage value) to the information output terminal 10.

As described above, the drains (or sources) of the MOS transistors in the memory blocks 218 to 21d whose gates are connected to the row decode outputs 4a to 4d are the same memory whose gates are connected to the column decode outputs 14a to 14d. The information to be stored is selected depending on whether it is connected to the source (or drain) of the MOS transistor in blocks 218 to 2-1d.

In this way, in this embodiment, the ROM is constructed using transistors arranged horizontally in the gate array as information storage and address selection transistors in the same column (or row). There is no need to provide a dedicated ROM area, and a ROM of any size can be efficiently formed within the gate array.

Furthermore, the number of storage blocks and the MOS in the storage blocks
) By increasing or decreasing the number of transistors along with the row and column addresses, it is possible to realize arbitrarily large ROMs in the gate array.

In the above embodiment, as shown in FIG.
This was done depending on whether or not the source (or drain) of the O3I transistor 15 i-151 was connected to the source (or drain) of the MO3I transistor 20a.
The storage information is distinguished as shown in Fig. 6.
Although the gates 5i to 151 are connected to the row decode outputs 4a to 4d, they may be connected to ground.

Further, in the above embodiment, the ROM is constructed using all the transistors arranged in a horizontal row, but it may be constructed using some of the transistors in the horizontal row. Furthermore, if a single horizontal row of transistors is insufficient, the ROM may be constructed using multiple rows of transistors.

Further, in the above embodiment, an example in which the present invention is applied to an N-channel MOS gate array has been described, but it may also be applied to a complementary MOS gate array, and the same effects as in the above embodiment can be obtained.

〔Effect of the invention〕

As described above, according to the semiconductor integrated circuit device according to the present invention, when a ROM is built into a gate array, the same column (
MO5I arranged on the same straight line in the gate array in the information storage transistor and address selection transistor of
- Since the ROM is configured using transistors, the ROM can be easily implemented within the gate array, there is no need to provide a dedicated ROM area, it can be mixed with logic elements, and LS
It is possible to achieve high usage efficiency and high integration of I.

[Brief explanation of the drawing]

FIG. 1 is a circuit configuration diagram of a conventional ROM, FIG. 2 is a configuration diagram of a gate array provided with a ROM dedicated area, FIG. 3 is a configuration diagram of a semiconductor integrated circuit device according to an embodiment of the present invention, and FIG.
The figure is a circuit diagram showing an example of a ROM formed in the device shown in FIG. 3, FIG. 5 is a circuit diagram excerpting a part of FIG. 4, and FIG. FIG. 3 is a circuit diagram showing another example of a ROM. l... Row decoder, 2, 3... Row address input, 4
a to 4d... Row decode output, 5a to 5d... Bit line, 5e... Common focus line, 6a to 6g, 7a to 7
d, 15 a to 151. 20 a・-N channel/
l, MOS transistor, 8... power supply terminal, 9...
Logic inversion type buffer, 10... information output terminal, 11.
12... Column address input, 13... Column decoder, 1
4a-14d... Column decode output, 16... Gate array chip 17... I10 buffer, 18... Logic circuit area, 19... ROM dedicated area, 21a-21
d...Memory block, 22...ROM main body. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.
Masuo Oiwa Figure 1 Figure 2 Figure 3 Figure 5 Figure 6

Claims (1)

[Claims] (11MO3) In a semiconductor integrated circuit device including a ROM constituted by transistors, the same column (
1. A semiconductor integrated circuit device characterized by an information storage transistor (or row). (2) The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device is a MOS gate array LSI consisting entirely of MO3) transistors of the same conductivity type.