JPS60244123A - Cmos master slice semiconductor device - Google Patents

Abstract

PURPOSE:To cope with two different working levels of a CMOS master slice semiconductor device having two types of input threshold voltage, by using a CMOS transistor which satisfies the specific conditions to constitute an input buffer circuit. CONSTITUTION:When the input voltage Vin is applied to a common gate through an input buffer circuit of a CMOSTR consisting of P and N channel transistors TR1 and 2, the threshold voltage values of the TR1 and 2 are set at VthP and VthN respectively. While the beta value of TR1 and 2 are set at betaP and betaN respectively together with the voltage VDD applied to a source electrode of the TR1. The coincidence is secured between channel currents of the TR1 and 2 for the threshold voltage value of a CMOS buffer circuit. Then two CMOS buffer circuits are used to obtain a CMOS master slice semiconductor device. When the logic threshold voltages are set at Vin1 and Vin2, the betaP and betaN are shown by equations I and II, respectively. Thus this semiconductor device can cope with two different working levels and is constituted definitely as TR, T1, T2 and T3, T4.

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a CMOS mask slice semiconductor device. In particular, the present invention relates to a CMOS mask slice semiconductor device that can configure an input buffer 7 circuit that can handle two different input levels, such as a TTL operating level and an 0MO5 operating level.・(2) Background of the technology and problems with the conventional technology Conventionally, at the beginning of the design of a CMOS master slice semiconductor device, the input is set to a TTL operating level (for example, +, jv).
or 0MO3 operating level (e.g. 2.5V)
The design is based on the premise that it will be possible to respond to either of these.

That is, in the prior art, CMOS which can be made both TTL compatible and CMOS compatible
There is no master slice semiconductor device, but as demand diversifies, there is a growing demand for a CMOS master slice semiconductor device that can configure an input buffer circuit in response to different input levels.

(3) Purpose of the invention The purpose of the present invention is to meet these demands.
An object of the present invention is to provide a CMOS master slice semiconductor device that can configure an input buffer 7 circuit that can handle two different input levels.

(4) Configuration of the invention The configuration of the invention is such that the logic threshold voltages are V, and v
In a CMOS mask slice semiconductor device that can handle two different input levels +nl and in2, where βP1 is the β value of the first P-channel transistor, and βNl is the β value of the first N-channel transistor. , vthPl is the threshold voltage of the first P-channel transistor, thNI is the threshold voltage of the first N-channel transistor, and vDD is the power supply voltage of the first P-channel transistor.

It's 0MO3) transistor that satisfies.

However, βP2 is the β value of the second P-channel transistor, and βN2 is the β value of the second N-channel transistor.

vthP2 is the threshold voltage and voltage of the first P-channel transistor.

vthN2 is the threshold voltage of the first N-channel transistor.

A second 0MO3) transistor that satisfies the following, and an input buffer 7 circuit is configured with either of the two 0MO3) transistors.

Or, out of the four transistors essential to this configuration, 2@ can be made exactly the same, so in that case, the required transistors are 4 (I
It is sufficient to use three instead of one, and it is possible to realize many benefits such as not only an improvement in the degree of integration but also a simplification of the manufacturing process.

0MO5) The input 87a circuit of the transistor is.

Generally, in the 0 diagram as shown in Figure 1, l is P
The channel transistor 2 is an N-channel transistor, and their gates are connected in common to which an input V is applied, and the train of the Pn channel transistor l and the train of the N-channel transistor 2 are commonly connected to the next It constitutes the connection terminal 3 with the stage inverter. vDD is connected to the source of P-channel transistor l, vss is N
Connected to the source of channel transistor 2.

By the way, in the above circuit, when the input voltage is equal to the logic threshold voltage, both the P-channel transistor 1 and the N-channel transistor 2 are f
1! It is in the Japanese area. and 0MO5) If the transistor is in the saturation region, the current ■ flowing through its channel. It is well known that is expressed by the following equation.

However, vo is the source-to-train voltage, - is the threshold voltage h of the transistor, and β is the β value of the transistor. It is also well known that the β value of the transistor is expressed by the following equation.

However, W is the channel width of the transistor, L is the channel length of the transistor, ε is the dielectric constant of the gate insulating film, and x t is the thickness of the gate insulating film. And x end. is the carrier mobility.

In the above circuit, the source-train voltage vDP applied to the P-channel transistor is VDρ″″′
Since vDD-v In , the current P flowing through that channel is.

・・・・・・・・・(3) however, βP is the β value of P-channel transistor 1.

Also, since the source-drain voltage vON applied to the N-channel transistor is vln, the current IDN flowing through the channel is...
・(4) However.

β, tiN channel transistor 2 βflI.

It is.

By the way, the logic threshold voltage of the CMOS input is determined by the channel current of the P-channel transistor l.
oP and channel current l of N-channel transistor 2
. Since this is the input voltage that makes N equal to N, equation (3) and (
4) From the equation, the condition of the following equation can be obtained.

Then, by transforming this, the following equation is obtained: Therefore, when the logic threshold voltage of the input circuit is vInl, the linear equation must be satisfied.

・・・・・・・・・(6) On the other hand, the logic threshold voltage of the input circuit is ■.

In2 If so, the following formula must be satisfied.

・・・・・・・・・(7)1 Therefore, a CMOS having both the first CMOS transistor that satisfies the above formula (6) and the second 0MO5) transistor that satisfies the above formula (7) The master slice semiconductor device also has an input level at which the logic threshold voltage is vlrll, and also has a logic threshold voltage at the input level v1.
It is also possible to cope with the input level n2 very easily by selectively forming the wiring.

(5) Embodiments of the invention Hereinafter, with reference to the drawings, a CMO according to an embodiment of the invention will be described.
The S master slice semiconductor device will be further explained.

Assuming that the input level shown in FIG.
o to 5v, ■ths to Ivthpl to 0.8■
Then, Equation 1 (6) is.

, and assuming that the input level is the operating level of TTL, its logic threshold voltage is 1.4V-t
If voDwo5v, vthN and 1vth, 1 are set to 0.8V, equation (7) becomes as follows.

Therefore, the first CMOS transistors T2, T2, in which βP/β, is l, and β, / /3, l) < 0.
A CMOS mask slice having second CMOS transistors T 1 and T 4 of 0.048 in the input buffer circuit section is manufactured. In the figure, 4 is an N+ region, 5 is a P+ region formed with a P well, and 6.7.
8.9.10 is a field insulating film. Is 11 the first CMO3? transistor p-channel transistor T,
15 is its gate. 12 is the N+ region of the N-channel transistor T2 of the first CMOS transistor, and 18 is its gate. +3
is the P'' region of the P-channel transistor T3 of the second CMOS transistor, and 17 is its gate.
14 is the N1 region of the N-channel transistor T of the second 0MO3) run star, and 18 is its gate.

Refer to FIGS. 3 and 4. Using the above CMOS mask slice semiconductor device,
In the case of MOS compatibility, the first CMOS transistor T is connected to each note shown in the block diagram of FIG.
, T2 to provide wiring as shown in FIG.

Refer to FIGS. 5 and 6. Using the above CMOS master slice semiconductor device,
In the case of TL compatibility, a second CMOS transistor T,
Using T, wiring as shown in FIG. 6 may be provided.

Refer to Figure 7.1 When designing two sets of CMOS transistors that satisfy equations (6) and (7), the P-channel transistor T
, T3 or N-channel transistors T, T4 may have the same structure. In that case, one set of identical transistors can be saved.

In FIG. 7, the common N-channel transistor is designated as T2, the P-channel transistor T and the N-channel transistor T2 constitute a first CMOS transistor, and the P-channel transistor T and the N-channel transistor T
As is clear from FIG. 0, which shows the case where the second CMOS transistor is configured with T and T, T is omitted.

Refer to FIGS. 8 and 9. Using the above CMOS mask slice semiconductor device,
In the case of MOS compatibility, wiring as shown in FIG. 9 may be provided using the first CMOS transistors T2 and T2 for each note shown in the block diagram of FIG.

Refer to FIGS. 10 and 11. Using the above CMOS master slice semiconductor device,
To make it TL compatible, use the second CMOS transistors T and T for each node shown in the block diagram of Fig. 1O, and provide wiring as shown in Fig. 11, 32°. good.

(6) As described in detail, according to the present invention, a CMO that can configure seven input buffer circuits that can handle two different input signals.
An S mask slice semiconductor device can be provided.

[Brief explanation of the drawing]

Figure W41 is a block diagram of the CMOS transistor input circuit. FIG. 2 is a plan view of a CMOS master slice semiconductor device according to an embodiment of the present invention, and FIGS. 3 and 4 are a block diagram and a plan view of a case where this is used to make it CMOS compatible. FIGS. 5 and 6 are a block diagram and a plan view of the case where this is used to achieve TTL compatibility. No. 7 @ is a CMO according to another embodiment of the present invention.
FIG. 8 is a plan view of the S master slice semiconductor device;
Fig. 9 is a block diagram and a plan view when this is used to make it CMOS compatible, and Figs. 10 and 11 are a block diagram and a plan view when this is used to make it TTL convertible. v1・Input voltage, V・・O power supply voltage, In DO V・・Ground voltage, No. 10・P channel S

Claims (2)

[Claims] (1) In a CMOS mask slice semiconductor device that can accommodate two different input levels with logic threshold voltages Vinl and Vin2, where βP1 is the β value of the first P-channel transistor, and βNl is the β value of the first P-channel transistor. is the β value of the N-channel transistor, vthPl is the threshold voltage of the first P-channel transistor, vthNl is the threshold voltage of the first N-channel transistor, and vDD is the power supply voltage of the first P-channel transistor. be. A first CMO3) transistor satisfying It's OK with the threshold voltage. (2) thN2 is the threshold voltage of the N-channel transistor of Fl. a second CMOS transistor that satisfies
A CMOS master slice semiconductor device comprising 27 circuits. (2) The CMOS master slice semiconductor device according to claim 1, wherein the first and second CMO transistors (3) have the same P-channel transistor or N-channel transistor.