JPS60245331A - Clock reproducing system - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Industrial Application Field The present invention relates to an improvement in a clock recovery method of a clock recovery circuit using a phase locked loop (PLL circuit) in a receiving device of a digital wireless communication device.

A receiving device of a digital wireless communication device reproduces a clock from a baseband signal, and uses this clock to reproduce a pulse code free of noise and distortion.

A phase-locked circuit is often used for this clock recovery circuit, but the frequency of the voltage-controlled oscillator in this phase-locked circuit is such that if the line is disconnected, the baseband signal clock will not be detected. It will no longer be the same.

However, as soon as the line is restored, it is desirable to pull in the baseband signal clock and regenerate the clock.

(b) Prior Art FIG. 2 is a block diagram of a conventional clock recovery circuit.

In FIG. 2, the baseband signal is amplified by an amplifier 1, a data clock is extracted by a bandpass filter 2, the amplitude of this extracted clock is limited by a limiter 3, and input to a phase comparator 4. and voltage controlled oscillator (V
The phase is compared with the clock output from the CO) 7, and the difference is amplified by the amplifier 5, converted to DC by the loop filter 6, and inputted to the voltage controlled oscillator 7, and the clock output from the voltage controlled oscillator 7. The frequency and phase of the baseband signal are controlled to be equal to the clock from the baseband signal,
I am trying to reproduce and output the clock.

(e) Problem to be solved by the invention However, in the circuit shown in FIG. 2, when the line is disconnected, the clock is not extracted from the bandpass filter 2, so the frequency of the clock output from the voltage controlled oscillator 7 is at the baseband. The signal's data clock frequency will no longer be the same.

Therefore, when the line is restored, there is a problem in that it takes time to bring in the baseband signal clock and equalize the frequency and phase.

(Means for solving d1 problem) The above problem is solved by providing a detector that detects line disconnection, and when line disconnection is detected, switching the control voltage of the voltage controlled oscillator of the phase locked circuit to a predetermined constant voltage. This problem is solved by the clock recovery method of the present invention.

(e) Effect In the present invention, a control voltage that makes the clock frequency of the voltage controlled oscillator almost the same frequency as the clock of the received data is set as a predetermined voltage, and if a line disconnection occurs, this is detected. , the control voltage of the voltage controlled oscillator is switched to the predetermined voltage, the frequency of the clock output from the voltage controlled oscillator is made almost the same as the clock of the received data, and when the line is restored, it is immediately switched to the clock of the received data. ,
By making the frequency and phase equal, the clock regeneration time is significantly shortened.

(f) Examples An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a clock recovery circuit according to an embodiment of the present invention.

In the figure, 8 is a level detector, SW is a switch, and ■ is a predetermined voltage, and the same symbols throughout the figures indicate the same functions.

In FIG. 1, when the line is normal, the switch SW is connected to the solid line side and performs the same operation as explained in FIG. 2.

When the line is disconnected, the level detector 8 detects this, connects the switch SW to the dotted line side, and switches the control voltage of the voltage controlled oscillator 7 to a predetermined voltage (2).

The predetermined voltage ■ is a predetermined control voltage that makes the frequency of the clock of the voltage controlled oscillator 7 almost the same as the clock of the received data, so even if the frequency of the clock of the voltage controlled oscillator 7 is switched, , is almost the same as the clock of the received data.

Therefore, when the line is restored and the switch SW is connected to the solid line side, the frequency and phase of the clock of the voltage controlled oscillator 7 immediately become equal to the clock of the received data, significantly shortening the clock regeneration time. are doing.

(g1 Effects of the Invention As described above in detail, the present invention has the effect of significantly shortening the clock regeneration time when the line is disconnected and restored.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a clock recovery circuit according to an embodiment of the present invention, and FIG. 2 is a block diagram of a conventional clock recovery circuit. In the figure, 1 and 5 are amplifiers, 2 is a bandpass filter, 3 is a limiter, 4 is a phase comparator, 6 is a loop filter, 7 is a voltage controlled oscillator, 8 is a level detector, SW is a switch, and V is a predetermined value. Indicates voltage.

Claims (1)

[Claims] A clock regeneration circuit using a phase-locked circuit in a receiving device of a digital wireless communication device is provided with a detector for detecting a line disconnection, and when a line disconnection is detected, the control voltage of the voltage-controlled oscillator of the phase-locked circuit is set to a predetermined value. A clock regeneration method characterized by switching to a constant voltage.