JPS6024701A - Microwave hybrid integrated circuit - Google Patents
Microwave hybrid integrated circuitInfo
- Publication number
- JPS6024701A JPS6024701A JP58133902A JP13390283A JPS6024701A JP S6024701 A JPS6024701 A JP S6024701A JP 58133902 A JP58133902 A JP 58133902A JP 13390283 A JP13390283 A JP 13390283A JP S6024701 A JPS6024701 A JP S6024701A
- Authority
- JP
- Japan
- Prior art keywords
- capacitor
- microwave
- thick film
- integrated circuit
- hybrid integrated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01P—WAVEGUIDES; RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE
- H01P7/00—Resonators of the waveguide type
- H01P7/08—Strip line resonators
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0237—High frequency adaptations
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/16—Printed circuits incorporating printed electric components, e.g. printed resistors, capacitors or inductors
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
Landscapes
- Waveguides (AREA)
Abstract
Description
【発明の詳細な説明】
この発明はセラミック基板を用いたマイクロ波混成集積
回路に関し、特に三端子マイクロ波半導体素子を厚膜コ
ンデンサにょシー電源で動作させるマイクロ波混成集積
回路に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a microwave hybrid integrated circuit using a ceramic substrate, and more particularly to a microwave hybrid integrated circuit in which a three-terminal microwave semiconductor element is operated by a thick film capacitor power source.
第1図(a)、第1図(b)および第1図(e)は従来
のマイクロ波混成集積回路を示す平面図、そのA −A
′断面図、およびそのB−i断面図である。同図におい
て、0)はマイクロ波帯において低誘電損失を有するセ
ラミックなどからなる誘電体基板、Q)はマイクロ波伝
送線路、(3)は低域通過フィルタ型のドレイン電極バ
イアス線路、(4)は低域通過フィルタ型のゲート電極
バイアス線路、6)はメタライズスルーホールによシ接
地されたソース接地電極、(6)は金線などのワイヤに
より各伝送線路に接続される三端子マイクロ波半導体素
子、σ)はマイクロ波帯において低豹電損失、高誘電率
を有するマイクロ波用チップコンデンサ、(8)は抵抗
値Rbの厚膜抵抗もしくはチップ抵抗などのバイアス抵
抗、(9)はメタライズスルーホールなどによシ接地さ
れた抵抗端接地電極、(10)は三端子マイクロ波半導
体素子(6)をマイクロ波伝送線路C2)およびマイク
ロ波用チップコンデンサ(7)に接続される金縁などの
ワイヤ、(11)はソース電極を抵抗を介して接地する
ソース電位電極、(12)は接地電極、(13)はメタ
ライズスルーホールである。FIG. 1(a), FIG. 1(b) and FIG. 1(e) are plan views showing a conventional microwave hybrid integrated circuit;
' sectional view and its B-i sectional view. In the figure, 0) is a dielectric substrate made of ceramic or the like that has low dielectric loss in the microwave band, Q) is a microwave transmission line, (3) is a low-pass filter type drain electrode bias line, and (4) (6) is a low-pass filter type gate electrode bias line, (6) is a source grounded electrode grounded by a metallized through hole, and (6) is a three-terminal microwave semiconductor connected to each transmission line by a wire such as a gold wire. element, σ) is a microwave chip capacitor with low electric loss and high dielectric constant in the microwave band, (8) is a bias resistor such as a thick film resistor or chip resistor with a resistance value Rb, and (9) is a metalized through-hole. A resistive end grounding electrode (10) is connected to the three-terminal microwave semiconductor element (6) to the microwave transmission line C2) and the microwave chip capacitor (7), which is connected to a wire such as a gold edge. , (11) is a source potential electrode that grounds the source electrode via a resistor, (12) is a grounding electrode, and (13) is a metallized through hole.
なお、第2図は第1図←)〜@1図(e)の電久的等価
回路でちる。In addition, FIG. 2 is based on the electrical equivalent circuit of FIG. 1←) to @1 (e).
次に上記構成によるマイクロ波混成集積回路の動作につ
いて説明する。まず、低域通過フィルタを構成するドレ
イン電極バイアスね路0)およびゲート電極バイアス抵
抗(4)を通して、三端子マイクロ波半導体素子(6)
に直流バイアスを印加すると、増幅器として動作する。Next, the operation of the microwave hybrid integrated circuit having the above configuration will be explained. First, the three-terminal microwave semiconductor element (6) is
When a DC bias is applied to it, it operates as an amplifier.
このとき、直流的にはソース電位Vsはドレイン−ソー
ス間電流IDSとバイアス抵抗(8)の抵抗値R1)の
Tt 、Vs = IDS x Rbだけ接地電位よシ
高くなυ、ゲートバイアスを接地することによシ、ソー
ス・ゲート間Vcsには′vGs= VS==−IDS
XRbのバイアスが印加する。また、マイクロ波的には
マイクロ波用チップコンデンサCI)を通して接地され
る。このため、1電源ソ一ス接地マイクロ波増幅器とし
て動作する。At this time, in terms of direct current, the source potential Vs is higher than the ground potential by Tt, Vs = IDS x Rb, which is the drain-source current IDS and the resistance value R1 of the bias resistor (8), υ, and the gate bias is grounded. In particular, the source-gate Vcs is 'vGs=VS==-IDS.
A bias of XRb is applied. Also, in terms of microwaves, it is grounded through a microwave chip capacitor CI). Therefore, it operates as a single power source grounded microwave amplifier.
しかしながら、従来のマイクロ波混成集積回路ではマイ
クロ波用チップコンデンサの取り付けにハンダ付などの
工程が必要であυ、さらに電気的接続に除し、金等のワ
イヤボンド工程が増加するなどの欠点があった〇
したがって、この発明の目的はチップコンデンサを実装
せず、基板上にコンデンサ構造を設けることにより、製
造工程を簡略化することができるマイクロ波混成集積回
路を提供するものである。However, in conventional microwave hybrid integrated circuits, processes such as soldering are required to attach microwave chip capacitors, and there are also disadvantages such as an increase in the process of bonding wires such as gold for electrical connections. Therefore, an object of the present invention is to provide a microwave hybrid integrated circuit which can simplify the manufacturing process by providing a capacitor structure on a substrate without mounting a chip capacitor.
このような目的を達成するため、この発明はセラミック
基板などの誘電体基板と、上部金属、絶縁物、下部金属
の三層から構成され、この下部金属がメタライズスルー
ホールで接地されて上記誘電体基板上に形成される厚膜
コンデンサと、この厚膜コンデンサの上部金属上にマウ
ントされる三端子マイクロ波半導体素子と、上記厚膜コ
ンデンサ″の上部金属と厚膜メタライズのバイアス抵抗
用端子とを接続する厚膜メタライズの線路とを備えるも
のであり、以下実施例を用いて詳細に説明する。In order to achieve such an object, the present invention consists of a dielectric substrate such as a ceramic substrate, and three layers: an upper metal, an insulator, and a lower metal, and the lower metal is grounded through a metalized through hole to connect the dielectric A thick film capacitor formed on a substrate, a three-terminal microwave semiconductor element mounted on the upper metal of the thick film capacitor, and a bias resistor terminal of the upper metal of the thick film capacitor and the thick film metallization. The device is equipped with a connecting thick-film metallized line, and will be described in detail below using examples.
第3図(a)、第3図(b)および第3図(c)はこの
発明である。同図において、(14)は低誘電損失を有
するセラミックなどの絶縁体、(15)はコンデンサ電
極として働く上部金属、(16)はこの上部金属(15
)とバイアス抵抗(8)の一端を接続する線路である。FIG. 3(a), FIG. 3(b) and FIG. 3(c) show this invention. In the figure, (14) is an insulator such as ceramic with low dielectric loss, (15) is an upper metal that acts as a capacitor electrode, and (16) is this upper metal (15).
) and one end of the bias resistor (8).
次に、上記構成によるマイクロ波混成集積回路の構成に
ついて説明する。まず、コンデンサの下部金属として働
くソース接地電極6)の下部金属。Next, the configuration of the microwave hybrid integrated circuit having the above configuration will be explained. First, the lower metal of the source ground electrode 6), which serves as the lower metal of the capacitor.
低誘電損失を有する絶縁体(14)およびコンデンサの
上部電極として働く上部金属の三層から厚膜コンデンサ
を形成することができるため、上述したように、1電源
ソ一ス接地マイクロ波増幅器として動作することはもち
ろんである。このため、第1図(a)〜第1図(c)に
示すチップコンデンサが不用になシ、製造工程を簡略化
することができる。As mentioned above, a thick film capacitor can be formed from three layers: an insulator (14) with low dielectric loss and a top metal that acts as the top electrode of the capacitor, thus operating as a single power source grounded microwave amplifier. Of course you can. Therefore, the chip capacitors shown in FIGS. 1(a) to 1(c) are not required, and the manufacturing process can be simplified.
なお、上述の実施例では三端子マイクロ波半導体累子と
して、電界効果トランジスタや接合型トランジスタなど
種々のトランジスタを用いることができることはもちろ
んである。In the above-described embodiments, it goes without saying that various transistors such as field effect transistors and junction transistors can be used as the three-terminal microwave semiconductor transistor.
以上詳細に説明したように、この発明に係るマイクロ波
混成集積回路によれば部品点数が減少し、作業工程が減
少するため、製造工程が簡略化され、信頼性を向上する
ことができる。また、厚膜コンデンサ構造はセラミック
多層基板技術により容易に作成することができるので実
用性が高いなどの効果がある。As described in detail above, according to the microwave hybrid integrated circuit according to the present invention, the number of parts and work steps are reduced, so that the manufacturing process can be simplified and reliability can be improved. Further, since the thick film capacitor structure can be easily created using ceramic multilayer substrate technology, it has the advantage of being highly practical.
第1図(a)、第1図中)および第1図(C)は従来の
マイクロ波混成集積回路を示す平面図、そのA −A断
面図およびそのn−i断面図、第2図は第1図(a)〜
第1図(e)の電気的等価回路、第3図(a)、第3図
中)および第3図(c)はこの発明に係るマイクロ波混
成集積回路の一実施例を示す平面図、そのC−C断面図
、およびD−D断面図、第4図は第3図(a)〜第3図
(e)の電気的等価回路である。
0)・・・・誘電体基板、(2)・・・・マイクロ波伝
送線路、G)・・・・ドレイン電極バイアス線路、(4
)・・Φ−ゲート電極バイアス線路、(5)・・・・ソ
ース接地電極、(6)・・・・三端子マイクロ波半導体
素子、(7)・・・・マイクロ波用チップコンデンサ、
(8)・・・・バイアス抵抗、(9)・・・・抵抗端接
地電極、(1G)・争・・ワイヤ、(11)・・拳・ソ
ース電位電極、(12)・・・・接地電極、(13)・
・・・メタライズスルーホール、(14)・・・・絶縁
体、(15)・・・・上部金属、(16)・・・・想路
。
なお、同一符号は同一または相当部分を示す。
代 理 人 大 岩 増 雄
第1図
(b)
i
第2図
第3図
(b)
]Z
第4図
特許庁長官殿
1.事件の表示 特願昭58−133902号2、発明
の名称 マイクロ波混成集積回路3、補正をする者
代表者片山仁へ部
4、代理人
明細書の発明の詳細な説明の欄
6、補正の内容
(1)明細書第2頁第17行の1−抵抗」を[バイアス
抵抗(8)」と補正する。
(2)同書第3頁第12行の「印加する」を「印加され
る」と補正する。
(3)同書第5頁第3行と第4行の間に次の文を加入す
る。
「なお、第4図は第3図(a)〜第3図(c)の電気的
等価回路を示す。」
以上
4FIG. 1(a), middle of FIG. 1) and FIG. 1(C) are a plan view showing a conventional microwave hybrid integrated circuit, its A-A cross-sectional view and its n-i cross-sectional view, and FIG. Figure 1(a)~
The electrical equivalent circuit of FIG. 1(e), FIG. 3(a), middle of FIG. 3) and FIG. 3(c) are plan views showing one embodiment of the microwave hybrid integrated circuit according to the present invention. The CC sectional view and the DD sectional view, FIG. 4, are electrical equivalent circuits of FIGS. 3(a) to 3(e). 0)... Dielectric substrate, (2)... Microwave transmission line, G)... Drain electrode bias line, (4
)...Φ-gate electrode bias line, (5)...source grounded electrode, (6)...3-terminal microwave semiconductor device, (7)...microwave chip capacitor,
(8)...Bias resistance, (9)...Resistance end ground electrode, (1G)...Wire, (11)...Fist/source potential electrode, (12)...Ground Electrode, (13)・
... Metallized through hole, (14) ... Insulator, (15) ... Upper metal, (16) ... Path. Note that the same reference numerals indicate the same or equivalent parts. Agent Masuo Oiwa Figure 1 (b) i Figure 2 Figure 3 (b) ]Z Figure 4 Mr. Commissioner of the Japan Patent Office 1. Indication of the case: Japanese Patent Application No. 58-133902 2, Title of the invention: Microwave hybrid integrated circuit 3, Representative Hitoshi Katayama of the person making the amendment: Section 4, Detailed description of the invention in the attorney's specification, column 6, Amendment Contents (1) "1-resistance" on page 2, line 17 of the specification is corrected to "bias resistance (8)". (2) "Apply" on page 3, line 12 of the same book is corrected to "apply". (3) Add the following sentence between the third and fourth lines of page 5 of the same book. "In addition, Figure 4 shows the electrical equivalent circuit of Figures 3(a) to 3(c)."
Claims (1)
メタライズスルーホールで接地されて上記誘電体基板上
に形成される厚膜コンデンサと、この厚膜コンデンサの
上部金属上にマウントされる三端子マイクロ波半導体素
子と、上記厚膜コンデンサの上部金属と厚膜メタライズ
のバイアス抵抗用端子とを接続する厚膜メタライズの線
路とを備えたことを特徴とするマイクロ波混成集積回路
。[Claims] A dielectric substrate such as a ceramic substrate and an upper metal. A thick film capacitor is composed of three layers: an insulator and a lower metal, and the lower metal is grounded through a metallized through hole to form the above dielectric substrate. A microwave hybrid integrated circuit comprising: a terminal microwave semiconductor element; and a thick film metallized line connecting the upper metal of the thick film capacitor and the thick film metallized bias resistor terminal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58133902A JPS6024701A (en) | 1983-07-20 | 1983-07-20 | Microwave hybrid integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58133902A JPS6024701A (en) | 1983-07-20 | 1983-07-20 | Microwave hybrid integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6024701A true JPS6024701A (en) | 1985-02-07 |
| JPS6361802B2 JPS6361802B2 (en) | 1988-11-30 |
Family
ID=15115768
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58133902A Granted JPS6024701A (en) | 1983-07-20 | 1983-07-20 | Microwave hybrid integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6024701A (en) |
-
1983
- 1983-07-20 JP JP58133902A patent/JPS6024701A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6361802B2 (en) | 1988-11-30 |
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