JPS6024730A - Down-edge detecting circuit using josephson device - Google Patents

Abstract

PURPOSE:To detect the down-edge of a current flowing to the primary winding of a transformer by varying the state of a resistance coupling type OR circuit constituted of a resistance and a Josephson device when said current is reduced to zero. CONSTITUTION:When the current of an input signal flowing through the primary winding of the transformer 101 increases from zero toward the direction as indicated with an arrow 121, the Josephson device 103 is switched to a resistance state at the time point when a branch current flowing through the Josephson device 103 of the secondary current induced in the direction as indicated with an arrow 122 in the secondary winding reaches a threshold level, and attenuates the current of the secondary winding of the transformer 101. Subsequently, said device is switched to a resistance zero state when the input signal current is reduced to zero from a prescribed value or the maximum value, its state is held, and the resistance coupling type OR circuit 102 is switched. Also, a resistance 104 connected in parallel to the Josephson device 103 operates mainly as a damping resistance against an equivalent capacity in the resistance state of the Josephson device 103, and also operates as a damping resistance against the inductance of the secondary winding of the transformer 101.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a logic circuit using a semiconductor device, and particularly to a latch circuit that detects a falling edge of an input current, and is known as a down edge detection circuit.

Various logic circuits using inductance coupling and various logic circuits switching by current injection have been proposed as logic circuits using digestive devices. However, since the logic circuit using the J6 Cefson device is a current control type circuit that controls switching on and off using current, there is a problem in that it is difficult to construct a negative circuit. Therefore, the latch circuit that detects the fall of the input current and stores the result (hereinafter referred to as the down edge detection circuit) is a mask slave logic circuit or a signal detection circuit of the side Sefson storage device (S, M, Faris+W, H, H).
Enke I s, E, N Vilsamakis a
nd H,H.

Zappe, J., B.M. J., Res., Devel.
op, + Vol, 24r Na2゜PP, 143
-PP, 154. March 1980).

Conventionally, JHD circuits (S, M,
Faris and A4 Davidson.

IEEE Trans, Niag,, Vol, MAG-
15, NL], PP 416-419. Jan, 1
979), a circuit that combines a transformer and a current injection quantum interferometer, and a down-edge power one-shot circuit constructed by connecting two stages of quantum interferometers with asymmetric thresholds (Kurosawa Itaru, Akihiko Yagi) , Nao Hayayo, Proceedings of the 43rd Annual Meeting of the Japan Society of Applied Physics % 28P' [J 10.PP
, 273.1982), etc. are known. However, these conventional down edge detection circuits are either magnetically coupled type interferometer switches that switch using inductance coupling, or
Since a current injection type vertical interferometer, which is composed of an inductance and a dielectric device and switches by current injection, is used as a latch circuit, the load from the input terminal becomes an inductance, so high-speed operation is difficult. In order to ensure that the latch circuit can obtain sufficient signal amplitude gain, the inductance of the quantum interferometer cannot be made small, so the area of the inductance part on one mask pattern becomes large, and the integration of the circuit by 1% becomes difficult. It had some serious drawbacks.

On the other hand, a resistance-coupled circuit is known as a D1Cefson circuit capable of high-speed operation and high integration, in which the circuit is composed of a resistor, a Josephson device, and a resistor.

It is an object of the present invention to eliminate the conventional down error described above. A resistor-coupled OR circuit consisting of a resistor and a di-coupled device connected through a series-connected diode device, and a resistor connected in parallel to the Josephson device, When the current flowing through the primary winding decreases to zero, the state of the resistor-coupled logic first circuit changes to obtain an edge detection circuit. Give a detailed explanation.

FIG. 1 shows a down edge detection circuit using a current injection type quantum interferometer known from 1995, which is used in a sense bus of a digital memory device.

The circuit of FIG. 1 includes a current injection type lazy interferometer 15 consisting of a diagonal Sefson device li, 12 and an inductance 13.14, a transformer 16 having a primary winding and a secondary winding. , a dielectric device 17 and a resistor 18 connected in series with each other to one terminal of the secondary winding of the transformer 16, and a dielectric device 17 and a resistor 18 connected directly to the other terminal of the secondary winding of the transformer 16. The device 17 and the transformer 16 are arranged to form a closed circuit with a resistor 19. Transformer 16
The primary winding of is connected to the sense line through terminals 2i and 22 b]
A bias current is supplied from the terminal portion 24 to the child interferometer 15 in a current injection type. As is clear from the above explanation, down edge detection circuits using conventional quantum interferometers require an inductance of 13.14, which makes high-speed operation difficult, and the inductance part makes it difficult to achieve high integration. The Cefson device 1 is connected in series between the coupled OR circuit 102 and the secondary winding of the transformer means 101 and the input terminal of the resistive coupled OR circuit j02.
03 and a resistor IQ4 connected in parallel to the second device 103.

An input signal is applied to terminals 105, 106 and energizes the primary winding of transformer means 101. Resistance-coupled logic circuit 1
02 is the conventionally known RCJLinQ rational sum circuit (J, 5one + T, Yoshida and)
L Abe.

Appl, Phys, Lett,, Vol, 40
．． Nα8. PP, 741-744, 1982) and the known JAW8 OR circuit (T, A.

Fulton, S.S., PeIand L+N.
Dunklet+erger+Appl, Phys,
Lett, Vol. 3.4. N [L 10.
PP, 709-PP.

711. 1979), etc., receives bias current from terminals 107 and 108, and sends output signals to terminals 109 and 110.

The Josephson device 103 is one of the transformer means 101.
When the input signal current flowing through the secondary winding increases from zero in the direction of arrow 121, a branch current flows through the diη Sefson device 103 of the secondary current induced in the secondary winding in the direction of arrow 122. switches to the resistive state when the threshold value is reached, attenuating the current in the secondary winding of the transformer means 101, and subsequently switches to the zero resistive state when the input signal current decreases from the specified or maximum value to zero. It functions as a nonlinear resistor that maintains that state and switches the resistor-coupled OR circuit 102. Here, the resistor 104 is 1 as described above.
0,,'-1 anti-104 is mainly di-Sefson device l
It acts as a damping resistance for the equivalent capacitance of o3 in its resistance state, and also acts as a damping resistance for the inductance of the secondary winding of the transformer hand 101. In addition, resistance tie type = 321! The sum circuit 102 is connected to the third circuit if necessary. A fourth negative bias terminal may be added to supply a negative bias current or the like.

In this embodiment, elements that are the same as circuit elements in FIG. 2 are designated by the same numbers and have the same functions. In the first embodiment, a 3-junction RCJL logic OR circuit 2Q1 composed of three Josephson devices 202 to 204 and resistors 205 to 2θ8 is used as a resistance-coupled OR circuit.

The down edge detection operation in the first embodiment is performed as follows. First input (before g is added,
The RCJL OR circuit 201 is set in consideration of the values of the terminal 107 and each element of the down edge detection circuit. Next, when the current of the input signal applied to terminals 105 and 106 increases from zero in the direction of arrow 121,
A secondary current is induced in the secondary winding in the direction of arrow 122. This secondary current flows in the direction opposite to the bias current through the switching gates of the RCJL OR circuit 201, and therefore the switching gates of the switching gates 203 and 204 do not switch. The CJL logic circuit also does not switch.On the other hand, the critical current value of the Josephson device 103
is set to a value smaller than the maximum value of the branch current of the secondary current flowing through the secondary current, so that during the rise of the secondary current, the Josephson device 103 switches to the resistive state and transfers the secondary current to the second branch current of the transformer means 101. It is attenuated to zero with a time constant approximately defined by the inductance of the next winding, the equivalent capacitance in the resistance state of the Josephson device 103, and the diving resistor 104. Transformer Means 101 (7) After the secondary current has attenuated to approximately zero, reducing the current of the input signal causes the secondary winding of the transformer means 101 to set arrow 122=103 to zero resistance state. At this time σ) - secondary current f, i:
, Josephson device 203゜・,♀04 which is the switching gate of RCJL OR circuit 20''
1ζ flow in the same direction as the mud, the critical current value of the Jisuga Sefson devices 203 and 204, the bias current and 2
Since it is set smaller than the sum of the maximum value of the next current,
The second Sefson devices 203, 204 switch to the resistance state before the secondary current increases further and reaches its maximum value. That is, the RCJL OR circuit 201 is designed to switch to the resistance state by the secondary current induced when the input signal current falls. Ji ■ Cefson Device 203.
When 204 switches to the resistance state, the resistor device 202 switches to the resistance state, and the output Kr1 appears on the output 9 and the output terminals 109 and 110.

After the Josephson devices 202-20.4 switch, the secondary current of the transformer means 101 is attenuated to zero with a time constant approximately determined by the resistor 205 and the circuit board of the Kumping resistor 104.

Here, the output signal can be taken out from terminals 107 and 108 depending on the case.

The down edge detection circuit is similarly reset by means known in the art for circuits using the JSefson device, that is, means for reducing the bias current to zero. on the other hand,
The magnetic flux initially trapped in the closed loop formed by the secondary 4-wire Toshiyaku Sefson device 103.2θ2.203 of the transformer means 10.2 performs an initial reset operation that causes the S-OR circuit 201 to switch once. This initial reset operation can be eliminated by applying a pseudo input signal to the terminals 105 and 106 or by applying a sufficiently large bias current to the terminals 107 and 108.

In the above explanation, it has been explained that the digital camera device 103 switches before the digital camera device 202 when the input signal current rises, but conversely, the digital camera device 7 device 202 switches first when the input signal current rises. The same result as above can be obtained by switching to . If the diW Sefson device 202 switches first, the secondary current in the direction of arrow 122 in the secondary winding of the transformer means lot is:
It attenuates to zero with a time constant determined by the parallel circuit of the D1 Cefson device 103 and the damping resistor 104 and the series circuit of the resistor 205. Subsequently, the input signal current 302.303
, a resistor 304 , and a third bias terminal 305 . The operation of the second embodiment of the down edge detection circuit using the JAWS logic utilization circuit 301 is performed in exactly the same manner as the first embodiment. That is, at the rise of the input signal current, the arrow 12 induced in the secondary winding of the transformer means 101
The secondary currents in two directions flow through the Jiposefson device 303, which is the switching gate of the JAW8 OR circuit 301, in the opposite direction to the bias current, so the JAWS OR circuit 3
Do not switch 01. Subsequently, the secondary current induced in the secondary winding of the transformer means 101 at the falling edge of the input signal current flows in the direction opposite to the direction of the arrow 122 through the G-type Sefson device 303 in the same direction as the bias current. When the sum of the secondary current and the bias current reaches the threshold value of the digital Sefson device 303, the digital Sefson device 303 is switched to the resistor 1 state. Sends output signal to G-Sefson device. The operation of the Jigifson device 103 and the transformer means 101 at the rising and falling edges of the input signal current, as well as the reset operation of the circuit and the removal of the trapped magnetic flux, are performed by the first OR circuit and the transformer means. , and the direction of the secondary current induced in the secondary winding at the rise of the signal current in the primary winding is opposite to the bias current of the resistor-coupled OR circuit, thereby creating a resistor-coupled OR circuit. By making it insensitive to the secondary current and attenuating the secondary current by inserting a nonlinear resistor composed of a diagonal Sefson device, the signal current is applied to the secondary winding side when the signal current subsequently falls. A secondary current flows in the opposite direction to that at the rise time, and this opposite secondary current is added to the bias current of the resistor-coupled OR circuit to switch the resistor-coupled OR circuit to prevent the down edge of the signal current. detecting and connecting in parallel to the Josephson device a damping resistor for the equivalent capacitance and the inductance of the secondary winding of the transformer means when the Josephson device is in the resistive state, In order to speed up the current attenuation by minimizing unnecessary oscillations at the time of attenuation, and to achieve high speed operation of the circuit and high R, Gheewa la and A- by using a resistor-coupled OR circuit.
Mukherjee; “Josephson direc
t coupled logic (DCL) + IH
DM 1979Tech, Dig, PP, 48
2 (1979)) and 4JL circuit (S.

Takada, 8. Kosaka, and H,H
ayakawa; 'Curr-ent Inje
ction Logic Gate with Fou
r Jose -phson Junctions+
” Japan, J, Appl, Phys.

5upp1.19-1. PP, 607 (1980), etc., and also includes other embodiments using well-known resistor-coupled OR circuits, and in these cases as well, the high-speed implementation of the present invention is implemented as in the first and second embodiments. The objectives of operation and high integration are achieved.

[Brief explanation of the drawing]

FIG. 1 shows a part of a sense bus of a storage device using a current injection quantum interferometer as an example of a conventionally known down edge detection circuit.・・・・Mayuko Jūrōkei, 16=・・・change, Seiki, 18. , 19...Resistance, 21.22.
...Signal input p-polarity, 23.24...Bias terminal/output terminal, 101...Transformer means, 102...Resistor-coupled OR circuit , 103・
...Josephson device for nonlinear resistance, 104
・・・・・・Dunning resistor, 105.106 ・・Param signal input terminal N 107.108 ・・Bias terminal, 109.110 ・・・・・Output terminal, ]2
1. Direction of current in the primary winding of the papa transformer means, 122
...direction of current in the secondary winding of the transformer means, 20
1... CJL theory;, ゛, sum circuit, 202, 203, 204... circuits constituting the OR circuit, Sefson de Noise, 205, 2
06゜207.208... Resistance island 301 forming the OR circuit... JAWS OR circuit, 30
2,303 =°°” Resistor forming the OR circuit, 304...- Resistor forming the OR circuit, 305°. Third bias terminal. [i8 01 years old lJ, fig.

Claims (1)

[Claims] transformer means having a primary winding and a secondary winding electromagnetically coupled to each other, and a resistor and a diW SEFT connected via a JIS device connected in series to said secondary winding; A resistor-coupled logical sum circuit consisting of a SON device and a resistor connected in parallel to a DIFFSON device connected in series to the secondary winding, and the current flowing through the primary winding.