JPS60247708A - programmable controller - Google Patents

Abstract

PURPOSE:To increase a processing speed by providing numbers of arithmetic circuits for parallel arithmetic. CONSTITUTION:A data transfer and an arithmetic instruction as control commands to a controlled system are read out of a storage device 2 which constitutes the programmable controller together with a transfer device 7, arithmetic unit 8, and I/O3 to fetch specified data by the data transfer device 7 through the I/O3, transfer the data to the device 7, transfer the arithmetic result of the device 8 to the I/O3, and control the output from the I/O3 to the controlled system. This device 8 is provided with numbers of arithmetic circuits 83 in parallel and arithmetic processes are carried out in parallel at a high speed. Consequently, the processing speed of the programmable controller is increased.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a processing method for a programmable controller, and particularly to a high-speed parallel processing method.

[Background of the invention]

A programmable controller is a type of computer that is used as a control device in general industry to control the opening and closing of valves, control the start and stop of motors, etc., and is applied in scales ranging from tens to thousands of input/output points to be controlled. There is. In addition, in terms of calculation speed, various options are available from low speed to high speed, but the need for high speed processing is increasing in particular. The first means of high speed processing is to shorten the instruction execution time of programmable controllers etc. The second method is to divide the processing among multiple programmable controllers. There is a limit to the reduction of instruction execution time, which is determined by the technological level of the logic circuits that can be employed.

Furthermore, the method of allocating processing by multiple controllers has problems such as complicating the system and increasing costs, so this is also not a decisive factor. Therefore, the demand for daytime speed processing requires the development of high-speed models. The prior art will be explained with reference to FIGS. 1 to 4.

FIG. 1 shows a system configuration diagram of a conventional programmable controller. 2 is a storage device that stores commands that are control instructions for the controlled object; 1 is a processing device that executes the instructions stored in the storage device 2; and 3 is an input/output device that executes input/output operations to the controlled object. .

Further explanation will be added regarding the processing device 1. 16 is a program color, the contents of which are applied to the storage device 2 and the input/output device 3 via an address bus 21; 14 is an instruction register in which instructions read from the storage device 2 are stored. A decoder 15 decodes the contents of the instruction register and issues an instruction to execute the instruction. 11 is an accumulator, which is a register for calculation. A temporary register 12 stores data when the contents of the accumulator 11 and other data are operated on.

13 is a computing unit that executes various operations according to instructions.

A control circuit 17 is a circuit that controls the entire processing device.

Typical operations of this programmable controller are as follows.

First, the program counter 16 outputs an address for reading an instruction to the storage device 2 to the address bus 21 . The storage device 2 outputs the contents of the designated address to the data bus 22. Data on the data bus 22 is stored in the accumulator 11 and the instruction register 14. The contents of the instruction register 14 are decoded by a decoder 15, and a calculation command is issued to the calculation unit 13. The arithmetic unit 13 executes arithmetic operations according to this command.

The operation of the programmable controller will be explained using the sequence circuit diagram in FIG. 2 and the program explanatory diagram in FIG.

The sequence shown in FIG. 2 can be expressed as follows. I
NI to IN and 40UT1 indicate input/output numbers.

OUT 1= ((IN 1) ten (IN2) ) ((I
N3)-(IN4)) In FIG. 3, PC indicates the value of the program counter. In PCO, the internal answer lNl0 is transferred to accumulator A. This is explained as A(INI). In PCI, the contents of the accumulator and IN2
Store the "sum" of the contents in the accumulator. In PC2, the contents of accumulator A are stored in working memory WMI. When the instructions are executed one after another in this way and the instruction of PN8 is executed, the operation result is output to 0UT1, and the sequence shown in FIG. 2 is no longer executed.

In this way, in conventional processing methods, the processing device transfers or performs calculations for each instruction, so the processing speed is determined by the execution time of the instruction, and it is not possible to significantly improve the processing speed. I can't hope.

FIG. 4 is an actual wiring diagram when the sequence shown in FIG. 2 is configured by hardware logic. In the figure, 3 is an input/output device, 8 is an arithmetic device, 9 is wiring between the input/output device 3 and the arithmetic device 8 or the arithmetic device terminals, and 83 is an arithmetic circuit constituting the arithmetic device. Since this circuit operates only with hardware, it is clear that it operates at high speed. However, this circuit requires wiring work when creating and changing the circuit, and is difficult to handle.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a high-speed processing programmable controller that employs a parallel calculation method and greatly increases processing speed.

[Summary of the invention]

The present invention provides a large number of arithmetic circuits capable of parallel operation, newly provides a function corresponding to wiring between the arithmetic circuits, realizes a parallel arithmetic system, and realizes high-speed processing and a programmable controller.

[Embodiments of the invention]

FIG. 5 is a system configuration diagram of the programmable controller of the present invention. 2 is a storage device in which transfer instructions are stored as shown in FIG. 8 is an arithmetic unit, which is composed of a large number of arithmetic circuits that can operate in parallel. 3 is an input/output device that executes input/output operations to the controlled object. 7 is a transfer device that reads the transfer instruction from the storage device 2 and sends it to the arithmetic unit 8.
Then, a transfer command is sent to the input/output device 3. The detailed configuration of the arithmetic device 8 will be explained. 83 is an arithmetic circuit; 82 is an arithmetic register that applies arithmetic data to the arithmetic circuit 83; 81 is an arithmetic decoder that selects the arithmetic register 82 specified by the address signal SA on the write address bus 102; and 84 is an address DA on the read address bus 101. A selector that selects the arithmetic circuit 83 specified by and reads out the arithmetic result.
− is.

The detailed configuration of the transfer device 7 is as follows. 74 is a program counter that reads the read address A for the storage device 2.
Output DDR. This address is sequentially incremented by 1 and updated. Reference numeral 72 is a write address register that stores a slot address indicating a transfer destination in the transfer command read from the storage device 2. A read address register 71 stores a read address indicating a transfer source in a transfer command read from the storage device 2. 73 is a timing signal generation circuit that outputs a write timing signal and a read timing signal.

Next, the operation of the inventive programmable controller will be explained with reference to FIGS. 5 to 8.

FIG. 6 is a time chart of the programmable controller of the present invention, and FIG. 7 is a sequence circuit diagram showing control example 2 of the programmable controller. The content of this sequence is to read data INI to IN4 from the input/output device, perform calculations, and store the results in the input/output device 0UT1.

Expressing the calculation contents as a formula, 0UT1=((INN)+(rN2)H(IN3)-(
IN4)) FIG. 8 is an explanatory diagram of a program that executes the sequence shown in FIG. 7.

The operation of executing the sequence shown in FIG. 7 according to the program shown in FIG. 8 will be explained with reference to FIGS. 5 and 6. Fifth
An address is output from the program counter 74 of the transfer device 7 shown in the figure. Let this address be the PC. As shown in FIG. 6, when this PC outputs the PCO, the storage device 2
The instruction is read from , the read address SA is sent to the read address register 72 of the transfer device, and the write address DA is sent to the write address register 71 of the transfer device.
is applied to the arithmetic unit 8 and the input/output device 3. This transfer command has the following sequence as shown in FIG.

INl, +1 This is an instruction to read the data at the INI address of the input/output device 2 and write it to the arithmetic circuit +1 of the arithmetic device 2. The input/output device 2 outputs the data DB at the address INI to the data bus 105 in accordance with the read timing signal 103 output from the transmission device 7. data bus 10
5 is a common bus for the arithmetic device 8 and the input/output device 3, so the output data DR of the input/output device is applied to the arithmetic device 8,
Write timing signal 103 output from the transfer device
R in the register 82 via the arithmetic decoder 81 in synchronization with
, EGI, and applied to the +1 terminal of the arithmetic circuit 83.

When the transfer is completed in this way, the program counter 4 of the transfer device is updated by +1 and the next transfer command is executed. When the program color progresses from 0 to 1, the "+" arithmetic circuit in Figure 7 is a new INI.

Start calculation with the data of IN2. Furthermore, when the program counter advances to 2.3, the "-" calculation circuit
N3. Start calculation with the data of IN4. In this way, when the program counter advances to 6, the sequence operation shown in FIG. 7 is completed, and the operation result is transferred to 0UT of the input/output device.
It is stored in 1.

As is clear from this operation, the more arithmetic circuits there are, the more parallel operation of the arithmetic circuits becomes possible, which contributes to high-speed processing.

Next, the processing speed of the programmable controller of the present invention will be explained. Since calculations are executed in parallel in hardware, the calculation speed is determined by the data transfer rate. The data transfer speed is determined by the time required to read instructions from the storage device 2 and the data transfer time between the arithmetic circuit 83 or between the arithmetic circuit 83 and the input/output device 3. Since high-speed elements can be applied to these circuits, high Vl and high transfer speed can be easily realized. Therefore, programmable
It is possible to speed up the processing of the controller.

〔Effect of the invention〕

According to the present invention, a high-speed processing programmable controller can be realized.

[Brief explanation of drawings]

Fig. 1 is a system configuration diagram of a conventional programmable threat controller, Fig. 2 is a sequence circuit diagram showing a control example of the programmable controller, Fig. 3 is an explanatory diagram of a program that executes the sequence shown in Fig. 2, and Fig. 4 is Fig. 2 is an actual wiring diagram of the sequence, Fig. 5 is a programmable controller diagram of the present invention, and Fig. 8 is a sequence circuit diagram showing another control example of the programmable controller. Fig. 8 is a program that executes the sequence of Fig. 7. It is an explanatory diagram. 1...processing device, 2...storage device, 3...input/output device, house 1 figure house 4 figure rate 5 figures also ■ figure graduation 80

Claims (1)

[Scope of Claims] 1. A storage device that stores commands such as data transfer and arithmetic operations that are control commands for a controlled object, and a storage device that reads and decodes the instructions stored in this storage device and performs data transfer and calculation according to the results. In a programmable controller consisting of a processing device that performs calculations, etc., and an input/output device that performs input/output operations to a controlled object, the processing device automatically outputs a specified output when an input signal is applied. A programmable controller comprising: an arithmetic device comprising a plurality of arithmetic circuits capable of parallel operation that output signals; and a transfer device that reads and executes instructions stored in the storage device. 2.4? - The programmable controller according to claim 1, characterized in that the instructions of the storage device consist of transfer instructions and do not include arithmetic instructions. 3. In claim 1, the transfer device reads an instruction stored in the storage device according to instructions from a program counter built into the transfer device, and reads out a data transfer source that is a command of the instruction. A programmable controller characterized in that an address and a data transfer destination address are output to the arithmetic unit and the input/output device to enable data transfer in -steps.