JPS6024954B2 - Electrochromic display electronic equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an electrochromic display electronic device.

Electrochromic display (hereinafter abbreviated as ECD)
) is known to have a so-called memory effect, in which the display state is maintained even after the applied voltage (or current) is removed.

By the way, in electronic devices using such ECD cells, it has been proposed to switch and display various information, such as hours, minutes, seconds, month, and day on an electronic clock, on one display. However, such a mode switching key ECD
If an interrupt occurs during cell erase or write timing, insufficient erasing, insufficient writing, or overwriting may occur, and the display of the ECD cell may not match the information of the new mode. The former particularly causes imbalance in display colors and significantly reduces display quality, and excessive writing
This increases the amount of charge per segment and increases the electrode potential difference between them, causing undesirable reactions and resulting in deterioration of the ECD cell. The present invention solves various drawbacks when switching modes as described above, and when switching modes, E
In addition to forcibly erasing the display of the CD cell, the ECD
The drive logic section of the device is set to a write standby state.

An embodiment of the present invention will be described below with reference to the drawings.

The embodiment is applied to an electronic watch, and FIG. 1 shows an overall block diagram. In FIG. 1, the oscillating section 1
The clock logic section 2 is similar to that used in conventional clocks, and the segment signal outputted from the clock logic section 2 is converted by the drive logic section 3 into logic for driving the ECD.

The drive section 4 is a drive signal generation circuit for the ECD cell 5. FIG. 2 shows a detailed block diagram of the drive logic unit 2 (per segment) in the partial elimination method, and FIG. 3 shows a time chart of signal waveforms of each part.

The D-type flip-flop FF inputs the segment signal Si to its D terminal and outputs it to the Q and Q terminals in synchronization with clock pulse 0.

The resistor R and capacitor C constitute a delay circuit, which delays the Q terminal signal Q by a predetermined time. This delayed signal Q
2 is connected to the AND gate A.2 via the inverter ln. , and the logic Q,,Q2 with the other Q terminal signal Q,
Take the Q terminal signal Q. Detect the rising edge of . Also, an AND gate A inputs the delayed signal Q2 and the Q terminal signal Q.
2 is logic Q. , Q2 and similarly detect the fall of the Q terminal signal Q. Now, if a segment signal Si as shown in FIG. 3 is input, and it is "0" for display state (W) and "1" for non-display state (E), then
Detection of a rise to "0" detects erasure of the ECD, and a fall to "0" detects writing of the ECD.Monomal vibrators MM, MM2 output erase detection signals Q., Q2 via OR gates OR. or write detection signal Q,,Q
2 is input, and an erase timing signal E and a write timing signal W are sequentially outputted to determine the period and timing for erasing and writing, respectively.

The latch circuit LA, inputs the erasure detection signals Q, , Q2 inverted by the inverter ln2 to the R terminal, and
An erase timing signal E is inputted to the terminal, and when erasure of the ECD is detected, the reset state is maintained during the erase timing signal E, and a set signal is outputted from the Q terminal as the segment erase control signal Si8.

On the other hand, the latch circuit L inputs the write signals Q, , Q2 inverted by the inverter ~ to the R terminal, and also inputs the write signals Q, Q2 inverted by the inverter~.
Erase timing signal E is applied to the terminal via OR gate OR2.
and write timing signal W are input, and when ECD writing is detected, it is reset between both timing signals E and W. Further, here, the Q terminal signal Q2 of the latch circuit LA2 and the write timing signal W inverted by the inverter ln4 are input to the OR gate OR3, and the IJ set signal only during the write timing signal W is extracted as the segment write control signal Siw. There is. As explained above, the erase timing signal E, write timing signal W, segment erase control signal Sic, and segment write control signal Siw are appropriately supplied to the drive circuit section 4 of FIG. 1 to erase any segment Si of the ECD cell 5. Or writing is performed. The mode signal generating section 6 generates a mode signal Mi in response to an externally operated switch (not shown), and arbitrarily selects the information being clocked by the timing logic section 2.

Then, the drive logic unit 3 is supplied with a segment signal Si corresponding to the information selected by the mode signal Mi. All segment erase control signal SailE, gate cutoff signal G
The set signal Set and the set signal Set are pulse signals among predetermined pulses generated when the mode signal Mi is switched, and are inputted to the drive logic section 3, gate 7, and drive section 4, respectively, and operate as follows. FIG. 4 is a time chart showing an example of the operation at this time. Note that FIG. 4 shows the segment signal Si that was in the display state (level "0") in both the old mode and the new mode at the time of cutting. The erase control signal Sa11E for all segments is inputted to the drive section 4, which causes the erase operation to be performed on all segments. A gate 7 interposed between the drive logic section 3 and the drive section 4 blocks the signal from the drive logic section 3 while the erase operation is being performed on all segments, and forcibly performs the above-mentioned erase operation. It is. That is, a pulse signal from the generator 6 is input to the gate 7 as a gate cutoff signal G, and the gate 7 is cut off in accordance with this pulse signal. The set signal Set is inputted to the D type flip-flop FF' of the drive logic section 4 shown in FIG.
1", and after that, when reading the segment signal Si at the "0" level, which is at least in the display state, the Q terminal signal Q is set to fall without fail, and the write detection signal Q is ,,Q2 are output.

The resulting segment write control signal Siw corresponds to all the write segment signals Si in the new mode that are input to the ○ type flip-flop FF, and is sent to the ECD cell 5 in accordance with the contents of the timing logic section 2 selected in the new mode. written. These devices are the same even if mode switching interrupts the erasing or writing timing of the ECD cell;
All the displays on the CD cells are once forcibly erased, and then the ECD drive logic section 3 is in a write standby state, so that it is possible to write to the ECD cells 5 in accordance with the contents selected in the new mode. can.

As described above, the present invention forcibly erases the display of the ECD cell at the time of mode switching and sets the ECD drive logic section to the write standby state.
Even if an interrupt occurs during the cell erase or write timing, insufficient erasing, insufficient writing, or overwriting will not occur, and the display will match the contents of the new mode afterwards, providing electronic devices with high practical value. can.

[Brief explanation of drawings]

FIG. 1 is an overall block diagram showing one embodiment of the present invention, and FIG.
The figure is a block diagram showing a specific example of the main part of Fig. 1, Fig. 3 is a time chart showing the signal waveforms of each part in Fig. 2, and Fig. 4 shows the signal waveforms of each part accompanying the operation of the circuit part of Fig. 1. This is a time chart. DESCRIPTION OF SYMBOLS 1... Oscillation part, 2... Timing logic part, 3... Drive logic part, 4... Drive part, 5... ECD cell, 6...
Mode signal generator, Mi...Mode signal, Sail
o: All segment erase control signal, G: Gate cutoff signal, Set: Set signal. Figure 1 Figure 4 Figure N Ship Figure 3

Claims (1)

[Claims] 1. A device for switching modes and displaying various information on one display body, comprising means for forcibly erasing the display of an ECD cell, and means for setting a drive logic section of the ECD to a write standby state, An electrochromic display type electronic device characterized by operating both of the above means when switching modes.