JPS6025255A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS6025255A JPS6025255A JP13410283A JP13410283A JPS6025255A JP S6025255 A JPS6025255 A JP S6025255A JP 13410283 A JP13410283 A JP 13410283A JP 13410283 A JP13410283 A JP 13410283A JP S6025255 A JPS6025255 A JP S6025255A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor substrate
- aluminum
- electrode
- film
- window
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 31
- 238000004519 manufacturing process Methods 0.000 title claims description 4
- 239000000758 substrate Substances 0.000 claims abstract description 24
- 238000000034 method Methods 0.000 claims abstract description 14
- 239000004020 conductor Substances 0.000 claims 1
- 229910052782 aluminium Inorganic materials 0.000 abstract description 16
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 16
- 229910052751 metal Inorganic materials 0.000 abstract description 10
- 239000002184 metal Substances 0.000 abstract description 10
- 238000007747 plating Methods 0.000 abstract description 8
- 230000001681 protective effect Effects 0.000 abstract description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 4
- 238000001259 photo etching Methods 0.000 abstract description 2
- 230000015556 catabolic process Effects 0.000 abstract 1
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- 238000001771 vacuum deposition Methods 0.000 abstract 1
- 239000010408 film Substances 0.000 description 17
- 238000007796 conventional method Methods 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 238000007738 vacuum evaporation Methods 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 230000009193 crawling Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
Landscapes
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は半導体装置に導電Ｎを形成する工程の中で、と
くに段差部ケまたいで導電層を形成する方法に関するも
のである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a process for forming a conductive layer in a semiconductor device, particularly to a method for forming a conductive layer across a step.
従来の半導体装置の例えば電極は、半導体基板の素子領
域を形成するＰ層あるいはＮ層の表面の一部に接触して
、更に基板及び素子領域を外部雰囲気から保護するため
の絶縁層（例えばシリコン酸化膜又はシリコン窒化膜）
の上にはい上がるように延在して形成されていた。その
ため、この絶縁保護膜の端部でその段差により電極の段
切れが生じたり、段差部で電極の厚さが薄くなり大電流
を流した時に段差部の電極が溶断するという事故が多か
った。For example, an electrode of a conventional semiconductor device is in contact with a part of the surface of a P layer or an N layer forming an element region of a semiconductor substrate, and is further coated with an insulating layer (for example, silicon) to protect the substrate and element region from an external atmosphere. oxide film or silicon nitride film)
It was formed by extending as if crawling above it. For this reason, there have been many accidents in which the electrode is broken due to the step at the edge of the insulating protective film, or the electrode becomes thinner at the step and the electrode at the step is fused when a large current is applied.
本発明は段切れ一？溶断のない電極構造を持つ半導体装
置の製造方法を提供することを目的とするものである。Is this invention one step at a time? It is an object of the present invention to provide a method for manufacturing a semiconductor device having an electrode structure that does not cause melting.
本発明の半導体装置の製造方法は、半導体基板の表面に
電極となる金属層を形成するにあたり。The method for manufacturing a semiconductor device of the present invention includes forming a metal layer to serve as an electrode on the surface of a semiconductor substrate.
第１の工程として、半導体基板上の保護膜に選択的に開
けられた窓に露出した半導体素子部に金属を例えばメッ
キ法を用いて付着させた後、第２の工程として、該半導
体基板の全面に金属層を形成することにより、保護膜の
端部での電極の段切れや電極の厚さの薄化を防止して大
電流駆動を可能できるという効果がある。As a first step, metal is attached to the semiconductor element portion exposed through a window selectively opened in a protective film on a semiconductor substrate using, for example, a plating method. Forming a metal layer over the entire surface has the effect of preventing breakage of the electrode at the end of the protective film and thinning of the electrode, thereby making it possible to drive with a large current.
以下に１本発明の一実施例を図面を用いて説明する。An embodiment of the present invention will be described below with reference to the drawings.
まず、半導体基板の表面に従来の方法？用いて電極とな
る金属を形成した場合の不具合点を説明する。従来の方
法は、写真蝕刻法を用いて窓を開けた保護膜としての５
ｉＯｚ膜２が形成されている半導体基板１（第１図に示
す）の上に、第２図に示すように電極となる金属として
、アルミニウム４を真空蒸着法？用いて１回の工程で全
面にこれを形成する。この方法では、ＳｉＯｘ膜２の端
部３の部分でアルミニウム４は段切れ５を起こしたり、
アルミ膜厚の薄い部分６が生じ大電流駆動した場合アル
ミニウム４が溶断してしまう事故が多かった。First, the conventional method on the surface of the semiconductor substrate? We will explain the disadvantages when using this method to form a metal that will become an electrode. The conventional method is to use photoetching to create a protective film with a window.
On the semiconductor substrate 1 (shown in FIG. 1) on which the iOz film 2 is formed, aluminum 4 is deposited by vacuum evaporation as a metal that will become an electrode, as shown in FIG. This can be formed on the entire surface in one step using the following methods. In this method, the aluminum 4 may break off 5 at the edge 3 of the SiOx film 2,
There were many accidents in which the aluminum film 4 melted down when a thin portion 6 of the aluminum film was generated and driven with a large current.
次に１本発明の一実施例を説明する。Next, one embodiment of the present invention will be described.
本発明による方法では、第１の工程として表面に写真蝕
刻法を用いて窓を開けた５ｉ０２膜２が形成されている
半導体基板１（第１図に示す）の表面ケメッキ液に接触
させ、メッキ液と半導体基板１の裏面との間に電圧をか
け、半導体基板１に形成されている素子にブレーク１り
゛ランを起こして電流を流し、窓の部分に露出した素子
に例えばアルミニウムのメッキを行ない 部での高さを
まず保証する。第３図はメッキが終了した時点の半導体
基板の断面図である。メッキが終了した後、第２の工程
として真空蒸着法でアルミニウム層８を半導体基板の表
面に形成する。アルミニウムを蒸着し終った時点の断面
図を第４図に示す。In the method according to the present invention, as a first step, the surface of a semiconductor substrate 1 (shown in FIG. 1) on which a 5i02 film 2 with a window formed by photolithography is formed is brought into contact with a plating solution, and the surface is plated. A voltage is applied between the liquid and the back surface of the semiconductor substrate 1, causing a break-1 run in the elements formed on the semiconductor substrate 1, and a current is applied to the elements exposed in the window area, for example, to plate the elements with aluminum. First, ensure the height in the conduct section. FIG. 3 is a cross-sectional view of the semiconductor substrate at the time when plating is completed. After plating is completed, as a second step, an aluminum layer 8 is formed on the surface of the semiconductor substrate by vacuum evaporation. FIG. 4 shows a cross-sectional view at the time when aluminum has been deposited.
本発明による方法の第１の工程においてメッキしたアル
ミニウム７によ、す、５ｉ０２膜２の端部３における段
差が緩和され、第２の工程において蒸着したアルミニウ
ム８には段切れや膜厚の薄い部分は生じない。The aluminum 7 plated in the first step of the method according to the invention alleviates the step difference at the edge 3 of the 5i02 film 2, and the aluminum 8 deposited in the second step has no step breaks or a thin film. No part occurs.
実験によると、メッキされたアルミニウム７の上面の高
さとＳｉＯｘ膜２の上面との高さの差が蒸着するアルミ
ニウム８の膜厚の±５０％以内に入っていれば、段切れ
や膜厚の薄い部分の発生を十分防止出来た。According to experiments, if the height difference between the top surface of the plated aluminum 7 and the top surface of the SiOx film 2 is within ±50% of the film thickness of the aluminum 8 to be vapor-deposited, there will be no breakage or thinning of the film. The occurrence of thin parts was sufficiently prevented.
尚、第１図、第２図、第３図、第４図共に半導体基板１
に形成されている素子領域は省略しである。Note that the semiconductor substrate 1 is shown in FIGS. 1, 2, 3, and 4.
The element regions formed in are omitted.
第１図は、電極となる金属層を形成する以前の半導体基
板の断面図、第２図は、従来の方法を用いて金属Ｒを形
成した半導体基板の断面図、第３図は本発明の一実施例
において、金属のメッキが終了した時点での半導体基板
の断面図、第４図は、本発明の一実施例が完了した時点
の半導体基板の断面図である。
１・・・・・・半導体基板、２・・・・・・５ｉｏ２膜
、３・・・・・・ｓｉｏ、膜の端部、４・・・・・・ア
ルミ、訃・・・・・段切れ。
６・・・・・・膜厚の薄い部分、７・・・・・・メッキ
したアルミ、８・・−・・・蒸着したアルミ。FIG. 1 is a cross-sectional view of a semiconductor substrate before forming a metal layer to become an electrode, FIG. 2 is a cross-sectional view of a semiconductor substrate on which a metal R is formed using a conventional method, and FIG. FIG. 4 is a cross-sectional view of the semiconductor substrate at the time when metal plating is completed in one embodiment. FIG. 4 is a cross-sectional view of the semiconductor substrate at the time when one embodiment of the present invention is completed. 1...Semiconductor substrate, 2...5IO2 film, 3...SIO, end of film, 4...Aluminum, end...Step Cut. 6... Part with thin film thickness, 7... Plated aluminum, 8... Vapor deposited aluminum.
Claims (1)
けられた窓の部分に導電体を付着させた後、第２の工程
として、該半導体基板の全面に導電層を形成することを
特徴とする半導体装置の製造方法。[Claims] For forming a conductive layer on the surface of a semiconductor substrate. In the first step, a conductor is attached to the window selectively opened in the insulating film on the semiconductor substrate, and then in the second step, a conductive layer is formed on the entire surface of the semiconductor substrate. A method for manufacturing a featured semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13410283A JPS6025255A (en) | 1983-07-22 | 1983-07-22 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13410283A JPS6025255A (en) | 1983-07-22 | 1983-07-22 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6025255A true JPS6025255A (en) | 1985-02-08 |
Family
ID=15120492
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13410283A Pending JPS6025255A (en) | 1983-07-22 | 1983-07-22 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6025255A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61293832A (en) * | 1985-06-21 | 1986-12-24 | Diafoil Co Ltd | Transparent, slippery biaxially oriented polyester film |
| JPH04159755A (en) * | 1990-10-23 | 1992-06-02 | Nec Kyushu Ltd | Semiconductor device |
| JPH0511884U (en) * | 1991-07-31 | 1993-02-19 | 邦晴 春名 | Foot wipe mat device for bathroom doorway |
-
1983
- 1983-07-22 JP JP13410283A patent/JPS6025255A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61293832A (en) * | 1985-06-21 | 1986-12-24 | Diafoil Co Ltd | Transparent, slippery biaxially oriented polyester film |
| JPH04159755A (en) * | 1990-10-23 | 1992-06-02 | Nec Kyushu Ltd | Semiconductor device |
| JPH0511884U (en) * | 1991-07-31 | 1993-02-19 | 邦晴 春名 | Foot wipe mat device for bathroom doorway |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPS6025255A (en) | Manufacture of semiconductor device | |
| JPH11121457A (en) | Method for manufacturing semiconductor device | |
| JP2717166B2 (en) | Method for manufacturing semiconductor device | |
| US5523187A (en) | Method for the fabrication of liquid crystal display device | |
| JP2750737B2 (en) | Method for manufacturing semiconductor device | |
| US6180495B1 (en) | Silicon carbide transistor and method therefor | |
| JPS5923523A (en) | Semiconductor device | |
| JP2959186B2 (en) | Method for manufacturing semiconductor device | |
| JPS62281356A (en) | Manufacture of semiconductor device | |
| JPS6223134A (en) | Method for manufacturing semiconductor integrated circuit device | |
| KR100305734B1 (en) | Manufacturing method of liquid crystal display device | |
| JP3750362B2 (en) | Method for forming dielectric thin film | |
| JPS6127898B2 (en) | ||
| JPS6226812A (en) | Manufacture of semiconductor device | |
| JPS5984442A (en) | Manufacture of semiconductor device | |
| JPS62222673A (en) | Schottky barrier type semiconductor device and manufacture thereof | |
| JPH0878523A (en) | Semiconductor device and manufacturing method thereof | |
| JPH063699A (en) | Manufacture of thin film semiconductor device | |
| JPS63117468A (en) | Manufacture of semiconductor device | |
| JPH0758410A (en) | Method for manufacturing semiconductor laser device | |
| JPS62221146A (en) | Semiconductor device | |
| JPH07193213A (en) | Manufacture of semiconductor device | |
| JPS60140847A (en) | Semiconductor device | |
| JPH0529352A (en) | Method of forming gate electrode for field effect transistor | |
| JPS6237967A (en) | Manufacture of semiconductor device |