JPS60254253A - Error information collecting circuit - Google Patents

Abstract

PURPOSE:To facilitate the easy pursuit of the cause of fault by separating errors of a RAM, and collecting the error-related information when said error separating job is over. CONSTITUTION:The film ware is read out of a specific RAM in a data processor and set to a data register 1'. Then a check circuit 2', detects errors. If an error is detected, an error recovery processing circuit 7 is started to separate the error information related to the RAM. When this separating job is over, a signal is transmitted through an AND circuit 8 and an OR circuit 10 to request the collection of fault information.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an error information collection circuit when a specific error is detected and the error is not immediately corrected when the error is detected.

With the recent remarkable progress in semiconductor technology, the use of firmware is being promoted even in large data processing devices. Firmware is implemented using a random access memory, and the response when an error occurs in the random access memory differs depending on each processing type.

For example, in a device that performs pipeline processing, the instruction analysis section can temporarily stop the pipeline even if an error is detected, and the error can be corrected during that time. However, in the calculation section, it is generally difficult to stop the pipeline, depending on the point at which the error is detected, so it is not necessary to always use the data after the error has been corrected. is preferred.

Furthermore, in recent large-scale data processing devices, when reading data, there are various readout modes. Partial reading, such as reading out a combination of byte data, is becoming more common.

In this case, without doing anything when an error is detected, for example, the error recovery processing circuit edits the partial word into a whole word, or performs error correction using an error correction code logic mechanism for each partial word. There is.

On the other hand, in order to make the hardware configuration more economical, it is not necessary to provide an error correction code logic mechanism (hereinafter referred to as FCC) for all error detection points. Depending on the need for speeding up, etc.
Currently, optimal error detection and correction mechanisms are used.

Therefore, in a part that uses an error detection mechanism that does not immediately collect the error at the time of error detection as described above, there is a possibility that there is insufficient information to analyze the cause of the error, such as a syndrome, at the time of error detection. The following problem occurs.

Even in such a case, a method is required that can collect sufficient error information to trace the cause of the error using the collected error information.

(bl Conventional Technology) Generally, when an error is detected in a data processing device, in order to collect information for analyzing the error,
Stop the clock of the data processing device as soon as possible,
Usually, the method is to collect internal information.

Figure 2 (a) shows an outline of the normal error handling mechanism. When data A is set in data register 1,
A check circuit (parity check, ECC check) 2 detects an error and sets the data in a data holding register 3 in order to save the data.

At this point, if an error is detected, the error signal is set in the error holding bit 4, and the output signal of the error holding bit 4 stops the clock of the data holding register 3, and the OR circuit 5 Through latch 6, restore state processing (RS) is activated.

In the restore state processing (R3), all clocks of the data processing device are stopped and a scan-out request is sent to an external device such as a service processor.

The service processor (not shown) activates a separately provided dedicated storage device (not shown) for collecting failure information, and stores information such as predetermined internal latches of the data processing device. It works to suck up the water at high speed. By separately analyzing the fault information stored in this storage device by a service processor or the like, the cause of the fault can be known.

The operation at this time is shown in a time chart as shown in Figure 2 (b).
DS is the timing to set data A to data register l, CHI is the timing to check and hold the error detection result in error holding bit 4, ER is the timing to collect all errors, and R is the timing to set data A to data register l.
3I~ shows the above-mentioned restore state processing (R5), in which, for example, at the timing of RS2, a clock stop request to the data processing device and a scan out request to an external device such as a service processor are sent.

This restore state processing (R3) is preprocessing for entering a machine check interrupt after the hard retry processing.

When the above-mentioned error information collection processing is completed, the data processing device generates a clock and enters error recovery processing according to an instruction from the service processor, for example.

10) Problems to be Solved by the Invention In this case, as described above, depending on the type of error or the detection method, sufficient error information may not be collected in the dedicated storage device.

For example, random access memory (hereinafter referred to as R^a) in which firmware of a data processing device is stored.
When data is read from the , the parity check circuit 2 performs an error check, and if an error is detected, the above-mentioned error recovery process includes a check in which the 1-bit error is corrected by ECC and rewriting is performed. In this method, there is a problem in that there is insufficient information for error analysis, such as in the information immediately after an error is detected, no syndrome bit has been generated yet, and the error bit is not known.

Furthermore, even when partial reading is performed, there is a problem in that the information available at the time when an error is detected is insufficient for error analysis.

In view of the above-mentioned conventional drawbacks, the present invention provides that when a specific error is detected for which there is insufficient information for the above-mentioned error analysis, the above-mentioned error recovery processing is started instead of immediately after the error is detected. According to the present invention, it is an object of the present invention to provide a method for collecting information of the data processing device according to instructions of the error recovery processing circuit after the error detection signal is detected as a specific error and as a normal error. M.W.
If an error classified as a normal error is detected, it will be processed as usual, but if the specific error mentioned above is detected, the clock of the error data holding register will be stopped immediately. , starts the error recovery processing circuit, separates the error information in the error recovery processing circuit, and when the separation is completed, issues a read request to the dedicated storage device, and at the same time starts the clock of the data processing device. stop. This is achieved by providing a method for canceling the stoppage of the clock and proceeding to normal processing at the time when a response signal (storage operation completion signal) is returned from the dedicated storage device.

(e) In other words, in the present invention, even if firmware data is read from, for example, 124M and an error is detected, the error bit is detected immediately by BCC.

If the specific error that is not corrected is detected, the error recovery processing circuit is activated, and in the error recovery processing, the error in the RAM is isolated;
Since the segment operates to collect related error information when the processing is completed, the cause of the failure can be easily traced by analyzing the error information by, for example, a service processor. There is.

lfl Example Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1(a) is a block diagram schematically showing an embodiment of the present invention, and FIG. 1(b) is a time chart showing its operation.

In the drawing, 5.6 is the same as that explained in Fig. 2, 1°, 2', 4''61 are functional blocks corresponding to 1 to 6 explained in Fig. 2, and 1'' is the same as that explained in Fig. 2. specific RA
A register for setting read data from M, 2' is a check circuit, 4' is a specific error holding bit, 6' is a launch, 7 to 10 are functional blocks necessary to implement the present invention, and 7 is an error recovery process. circuit (However, as mentioned above, this circuit is also used in the error recovery process after error information collection in the conventional method, and in the present invention, the retry function in this circuit and error bit detection by ECC are used.

The point is to focus on the correction function, etc., and use this circuit to isolate RAM-related error information before collecting error information), 8 is an AND circuit, and 9.10 is an OR circuit.

Now, when the firmware is read from a specific RAl'l in the data processing device and set in the data register 1', error detection is performed by the check circuit 2'.

At this point, if an error is detected, the error signal is set in the specific error holding bit 4', and the error recovery processing circuit 7 is activated by the output signal of the specific error holding bit 4'. The signal is set in the latch 6' and passes through the OR circuit 9 to enter the restore state processing (RS) explained in FIG.

In the error recovery processing circuit 7, in addition to correcting error bits using ECC necessary for recovery, the error recovery processing circuit 7 uses a retry function to correct the above-mentioned R necessary for implementing the present invention.
Isolate AM-related error information.

For example, when an error is detected, even if only a parity check is performed and the read data is not completely saved, a syndrome bit is generated using ECC to determine which bit is in error. Error bits can be localized.

Once the error information has been isolated as described above, a signal 11EQ requesting the dedicated storage device (not shown) to collect (scan out) the fault information is sent, and at the same time, the data processing device Stop the clock. [That is, R32 of the above restore state processing (R3)
] In FIG. 1, this operation is performed by the AND circuit 8. in response to the scan-out request signal RIEQ. It is executed through an OR circuit 10. At this time, all information and the like for the above error information are stored.

Then, when a fault information collection completion signal is returned from the dedicated storage device, the stoppage of the clock is canceled and the data processing device is controlled to return to normal processing.

Thereafter, the service processor reads the fault information from the dedicated storage device and analyzes it to determine the details of the fault in the same manner as in the case of normal errors. Analysis will be possible.

If the error detected when reading the firmware of the data processing device is a normal error (that is, an error in an error detection circuit that has a function to immediately correct error bits), the second Same operation as explained in the figure, that is, the OR circuit 5. in FIG. 1(a). latch 6
The restore state processing (R
5) can be entered.

A time chart showing the above operation is shown in Figure 1 (
(b), DS, CIIK, R3I~ show the same operation as that explained in Figure 2 (a), and SEP
is an operation corresponding to ER in FIG. 2(A), and indicates that the S[P is a specific error that requires implementation of the present invention.

1. The operation according to the present invention is characterized in that the stage R81 of the restore state processing (R3) is waited until the response signal REQ is returned from the error recovery processing circuit 7.

The operations after the RSI stage (from R52) are the same as in the conventional system, and the timing of R32 is the clock stop request and scan-out request timing.

(Effects of the Invention As explained in detail above, the error information collection circuit of the present invention classifies error detection signals into specific errors and normal errors, and detects those classified as normal errors. If the above specific error is detected, the error recovery processing circuit is started using the latch information that detected the specific error, and the error recovery processing circuit is processed as before. The information is divided, and when the division is completed, a read request is issued to the dedicated storage device and at the same time the clock of the data processing device is stopped. When the operation completion signal (operation completion signal) is returned, the stoppage of the clock is canceled and normal processing begins, so the information immediately after an error is detected does not contain information for error analysis. Also, if a specific error is detected that results in a shortage.
It has the effect of collecting sufficient information for error analysis.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an outline of an embodiment of the present invention using a block diagram and a time chart. FIG. 2 is a diagram showing an outline of the conventional system using a block diagram and a time chart. In the drawing, '1 is a data register, and 2 is a check circuit. 3.3' is a data holding register. 4.4' is an error holding bit. 5 is an OR circuit, 6, 6" is a latch. 7 is an error recovery processing circuit. 8 is an AND circuit, and 9.10 is an OR circuit. S is a data set timing. CH is a check and error detection result retention timing. ER and SEP are timings to summarize all errors. R5I~ are restore state processing (R5) timings. REQ is an error recovery processing completion signal. 5

Claims (1)

[Claims] A plurality of error detection means for detecting errors, an error information holding register whose clock is stopped by the output of the error detection means, an error recovery processing circuit activated by the output, and a latch that can be scanned out. A data processing device comprising a storage means for collecting and storing the latch information, and a means for immediately stopping a clock of the processing device when a normal error is detected, and collecting and storing the latch information in the storage means. 1. When a specific error is detected, the data processing device has a function of stopping the clock of the data processing device and collecting and storing information of the latch in accordance with instructions from the recovery processing circuit. Error information collection circuit.