JPS60257550A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS60257550A
JPS60257550A JP59115879A JP11587984A JPS60257550A JP S60257550 A JPS60257550 A JP S60257550A JP 59115879 A JP59115879 A JP 59115879A JP 11587984 A JP11587984 A JP 11587984A JP S60257550 A JPS60257550 A JP S60257550A
Authority
JP
Japan
Prior art keywords
bonding pad
insulating film
semiconductor device
residue
etching
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59115879A
Other languages
Japanese (ja)
Inventor
Satoru Kishida
悟 岸田
Kazuhiro Sakashita
和広 坂下
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP59115879A priority Critical patent/JPS60257550A/en
Publication of JPS60257550A publication Critical patent/JPS60257550A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/921—Structures or relative sizes of bond pads
    • H10W72/922—Bond pads being integral with underlying chip-level interconnections
    • H10W72/9226—Bond pads being integral with underlying chip-level interconnections with via interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/921—Structures or relative sizes of bond pads
    • H10W72/923—Bond pads having multiple stacked layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H10W72/934—Cross-sectional shape, i.e. in side view
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/981—Auxiliary members, e.g. spacers
    • H10W72/983—Reinforcing structures, e.g. collars

Landscapes

  • Wire Bonding (AREA)

Abstract

PURPOSE:To prevent the generation of movable residue in a first bonding pad due to etching on the formation of a second bonding pad by coating the first bonding pad with the second bonding pad, which must be superposed on the first bonding pad. CONSTITUTION:In a device with a first bonding pad formed onto the required section of the surface of an insulating film shaped onto the main surface of a semiconductor substrate and a second bonding pad formed so as to be superposed to the first bonding pad, the generation of movable residue in the first bonding pad due to etching on the formation of the second bonding pad 6b can be prevented because the second bonding pad 6b is shaped so as to coat the first bonding pad 3, thus resulting in no adhesion onto a wiring film of residue, then improving the yield of products.

Description

【発明の詳細な説明】 〔発明の技術分野〕 この発明は半導体基板の主面上に形成された絶縁膜の表
面の所要部分上に形成された第１のポンディングパッド
とこの第１のポンディングパッドに重ね合わされるよう
に形成された第２のポンディングパッドとを有する半導
体装置に関するものである。Detailed Description of the Invention [Technical Field of the Invention] The present invention relates to a first bonding pad formed on a predetermined portion of the surface of an insulating film formed on a main surface of a semiconductor substrate; The present invention relates to a semiconductor device having a second bonding pad formed to overlap the bonding pad.

〔従来技術〕[Prior art]

第１図は従来の半導体装置の一例のポンディングパッド
の部分を示す要部断面図である。FIG. 1 is a sectional view of a main part showing a bonding pad portion of an example of a conventional semiconductor device.

図において、（１）は半導体基板、（２）は半導体基板
（１）の主面上に形成された絶縁膜、（３）は絶縁膜（
２）の表面の所要部分上に形成された第１の配線膜の一
部分である第１のポンディングパッド、（４）は第１の
ポンディングパッド（３）を含む上記第１の配線膜の表
面上および絶縁膜（２）の表面上にわたって形成された
眉間絶縁膜、（５）は層間絶縁膜（４）の第１のポンデ
ィングパッド（３）の上の部分に設けられた第１のコン
タクトホール、（６）は眉間絶縁膜（４）の表面の所要
部分上に形成された第２の配線膜の一部分であシ第１の
コンタクトホール（５）を通して第１のポンディングパ
ッド（３）の表面上に重ね合わされた第２のポンディン
グパッド、（７）は第２のポンディングパッド（６）を
含む上記第２の配線膜の表面上および′層間絶縁膜（４
）の表面上にわたって形成された表面保護用絶縁膜、（
８）は表面保護用絶縁膜（７）の第２のポンディングパ
ッド（６）の上の部分に設けられた第２のコンタクトホ
ールである。In the figure, (1) is a semiconductor substrate, (2) is an insulating film formed on the main surface of the semiconductor substrate (1), and (3) is an insulating film (
2) a first bonding pad that is a part of the first wiring film formed on a required portion of the surface of the first wiring film; The glabella insulating film (5) is formed on the surface and over the surface of the insulating film (2). The contact hole (6) is a part of the second wiring film formed on a required part of the surface of the glabella insulating film (4). ), (7) is superimposed on the surface of the second wiring film including the second bonding pad (6) and the interlayer insulating film (4).
), a surface protection insulating film formed over the surface of (
8) is a second contact hole provided in a portion of the surface protection insulating film (7) above the second bonding pad (6).

ところで、この従来例では、第２のポンディングパッド
（６）の表面の第１のコンタクトホール（５）に面する
端面に対応する部分に段差ができるので、第２のポンデ
ィングパッド（６）の表面にボンディングワイヤ（図示
せず）を接続するときに、第２のポンディングパッド（
６）の上記段差の部分にクラックが発生しやすいという
欠点があった。By the way, in this conventional example, since a step is formed on the surface of the second bonding pad (6) at a portion corresponding to the end surface facing the first contact hole (5), the second bonding pad (6) When connecting a bonding wire (not shown) to the surface of the second bonding pad (
6) There was a drawback that cracks were likely to occur at the step portion.

そこで、かかる欠点を除去するために、層間絶縁膜が第
１のポンディングパッドの表面上に形成されていないよ
うにすることによって、第１のポンディングパッドの表
面上に形成される第２のポンディングパッドの表面が平
坦になるようにした先行技術による半導体装置が提案さ
れている。Therefore, in order to eliminate such defects, the interlayer insulating film is not formed on the surface of the first bonding pad, so that the second bonding pad is formed on the surface of the first bonding pad. Prior art semiconductor devices have been proposed in which the surface of the bonding pad is flat.

第２図はこの先行技術による半導体装置のポンディング
パッドの部分を示す要部断面図である。FIG. 2 is a sectional view of a main part showing a bonding pad portion of a semiconductor device according to this prior art.

図において、第１図に示した符号と同一符号は同等部分
を示す。（５ａ）は層間絶縁膜（４）の第１のポＩ　ン
デイングパツド（３）の上の部分およびこれに接す１　
る部分を取シ除いて設けられ第１のポンディングパッド
（３）の周縁より外側に周縁を有する第１のコンタクト
ホール、（６ａ）は第１のボンディングパラ）”　（３
１Ｏ表面上に形成され第１のポンディングパッド（３）
の周縁と同一位置に周縁を有する第２のポンディングパ
ッドである。In the figure, the same symbols as those shown in FIG. 1 indicate equivalent parts. (5a) is the first point of the interlayer insulating film (4) above the bonding pad (3) and the first point in contact therewith.
A first contact hole (6a) is provided by removing a portion of the first bonding pad (3) and has a periphery outside the periphery of the first bonding pad (3).
A first bonding pad (3) formed on the 1O surface.
a second bonding pad having a periphery at the same location as the periphery of the pad;

この先行技術による半導体装置では、第１のコンタクト
ホール（５ａ）の周縁が第１のポンディングパッド（３
）の周縁より外側にあるので、第１のポンディングパッ
ド（３）の表面上に眉間絶縁膜（４）が形成されていな
い。従って、第２のポンディングパッド（６ａ）の表面
が平坦になるので、第２のポンディングパッド（６ａ）
の表面にボンディングワイヤ（図示せず）を接続すると
きに、第１図に示した従来例のように、第２のポンディ
ングパッド（６ａ）にクラックが発生するおそれがない
。In the semiconductor device according to this prior art, the periphery of the first contact hole (5a) is connected to the first bonding pad (3).
), the glabellar insulating film (4) is not formed on the surface of the first bonding pad (3). Therefore, since the surface of the second bonding pad (6a) becomes flat, the second bonding pad (6a)
When a bonding wire (not shown) is connected to the surface of the second bonding pad (6a), there is no risk of cracks occurring in the second bonding pad (6a) as in the conventional example shown in FIG.

しかし、第２のポンディングパッド（６ａ）の周縁が第
１のポンディングパッド（３）の周縁と同一位置にある
ので、第２のポンディングパッド（６ａ）　ト第１のポ
ンディングパッド（３）との間にパターンずれが生じた
場合には、第２のポンディングパッド（６ａ）の形成時
のエツチングによって第１リボンデイングパツド（３）
の一部がエツチングされて移動可能な残留物になる。こ
の第１のポンディングパッド（３）のエツチングにより
生じた移動可能な残留物が、層間絶縁膜（４）の表面上
に形成されている第２の配線膜の第２のポンディングパ
ッド（６ａ　）　ノｍ　分収外に付着して製品歩留りを
低下させるという欠点があった。However, since the periphery of the second bonding pad (6a) is located at the same position as the periphery of the first bonding pad (3), the second bonding pad (6a) and the first bonding pad (3) ), if a pattern misalignment occurs between the first ribbon bonding pad (3) and the first ribbon bonding pad (3) due to etching during formation of the second bonding pad (6a).
A portion of the material is etched into a movable residue. The movable residue generated by etching the first bonding pad (3) is transferred to the second bonding pad (6a) of the second wiring film formed on the surface of the interlayer insulating film (4). ) There was a drawback that it adhered to the outside of the fraction and lowered the product yield.

〔発明の概要〕[Summary of the invention]

この発明は、上述の欠点を除去するためになされたもの
で、第１のポンディングパッドをこれに重ね合わせる第
２のボンディングパットテ覆うようにすることによって
、第２のポンディングパッドの形成時のエツチングによ
る第１のポンディングパッドの移動可能な残留物が発生
するのを防止して製品歩留シを向上させることができる
半導体装置を提供するものである。This invention has been made to eliminate the above-mentioned drawbacks, and by covering the first bonding pad with the second bonding pad superimposed thereon, the second bonding pad is covered with the second bonding pad. An object of the present invention is to provide a semiconductor device that can improve product yield by preventing the generation of movable residue on a first bonding pad due to etching.

〔発明の実施例〕[Embodiments of the invention]

第３図はこの発明の一実施例の半導体装置のポンディン
グパッドの部分を示す要部断面図である。FIG. 3 is a sectional view of a main part showing a bonding pad portion of a semiconductor device according to an embodiment of the present invention.

図において、第１図および第２図に示した符号と同一符
号は同等部分を示す。（６ａ）は第１のポンディングパ
ッド（３）を覆うように形成された第２のポンディング
パッドである。In the figures, the same symbols as those shown in FIGS. 1 and 2 indicate equivalent parts. (6a) is a second bonding pad formed to cover the first bonding pad (3).

この実施例では、第２のポンディングパッド（６ｂ）が
第１のポンディングパッド（３ンを覆うように形成され
ているので、第２のポンディングパッド（６ｂ）の形成
時のエツチングによる第１のポンディングパッド（３）
の移動可能な残留物が発生するのを防止することができ
、残留物の配線膜への付着がなくなり、製品歩留りの向
上を図ることができる。In this embodiment, since the second bonding pad (6b) is formed to cover the first bonding pad (3), the etching effect during formation of the second bonding pad (6b) 1 pounding pad (3)
The generation of movable residues can be prevented, and the residues will no longer adhere to the wiring film, making it possible to improve product yield.

〔発明の効果〕〔Effect of the invention〕

以上、説明したように、この発明の半導体装置では、第
１のポンディングパッドをこれに重ね合わせる第２のポ
ンディングパッドで覆うようにしたので、第２のポンデ
ィングパッドの形成時のエツチングによる第１のポンデ
ィングパッドの移動可能な残留物が発生するのを防止す
ることができ、残留物の配線膜への付着がなくなり、製
品歩留りの向上を図ることができる。As explained above, in the semiconductor device of the present invention, the first bonding pad is covered with the second bonding pad superimposed thereon, so that the etching caused by the formation of the second bonding pad is It is possible to prevent the generation of movable residue on the first bonding pad, eliminate the adhesion of the residue to the wiring film, and improve product yield.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は従来の半導体装置の一例のポンディングパッド
の部分を示す要部断面、第２図は先行技術による半導体
装置のポンディングパッドの部分を示す要部断面図、第
３図はこの発明の一実施例の半導体装置のポンディング
パッドの部分を示す要部断面図である。 図において、（１）は半導体基板、（２）は絶縁膜、（
３）は第１のポンディングパッド、（６ｂ）は第１のポ
ンディングパッド（３）を覆うように形成された第２の
ポンディングパッドである。 なお、図中同一符号はそれぞれ同一または相当部分を示
す。 代理人　大岩増雄 第１図FIG. 1 is a cross-sectional view of a main part showing a bonding pad part of an example of a conventional semiconductor device, FIG. 2 is a cross-sectional view of a main part showing a bonding pad part of a semiconductor device according to the prior art, and FIG. 3 is a cross-sectional view of a main part showing a bonding pad part of an example of a conventional semiconductor device. FIG. 2 is a cross-sectional view of a main part showing a bonding pad portion of a semiconductor device according to an embodiment. In the figure, (1) is a semiconductor substrate, (2) is an insulating film, (
3) is the first bonding pad, and (6b) is the second bonding pad formed to cover the first bonding pad (3). Note that the same reference numerals in the figures indicate the same or corresponding parts. Agent Masuo Oiwa Figure 1

Claims (1)

【特許請求の範囲】[Claims] （１）半導体基板の主面上に形成された絶縁膜の表面の
所要部分上に形成された第１のポンディングパッドと、
この第１のポンディングパッドに重ね合わされるように
形成された第２のポンディングパッドとを有するものに
おいて、上記第１のポンディングパッドを上記第２のポ
ンディングパッドで覆うようにしたことを特徴とする半
導体装置。(1) a first bonding pad formed on a required portion of the surface of an insulating film formed on the main surface of the semiconductor substrate;
and a second bonding pad formed so as to be superimposed on the first bonding pad, wherein the first bonding pad is covered with the second bonding pad. Characteristic semiconductor devices.
JP59115879A 1984-06-04 1984-06-04 Semiconductor device Pending JPS60257550A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59115879A JPS60257550A (en) 1984-06-04 1984-06-04 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59115879A JPS60257550A (en) 1984-06-04 1984-06-04 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS60257550A true JPS60257550A (en) 1985-12-19

Family

ID=14673432

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59115879A Pending JPS60257550A (en) 1984-06-04 1984-06-04 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS60257550A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02251158A (en) * 1989-03-24 1990-10-08 Nec Corp Semiconductor device

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5315759A (en) * 1976-07-28 1978-02-14 Hitachi Ltd Electronic parts
JPS5619639A (en) * 1979-07-27 1981-02-24 Hitachi Ltd Semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5315759A (en) * 1976-07-28 1978-02-14 Hitachi Ltd Electronic parts
JPS5619639A (en) * 1979-07-27 1981-02-24 Hitachi Ltd Semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02251158A (en) * 1989-03-24 1990-10-08 Nec Corp Semiconductor device

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