JPS60257559A - CMOS integrated circuit device - Google Patents
CMOS integrated circuit deviceInfo
- Publication number
- JPS60257559A JPS60257559A JP59114202A JP11420284A JPS60257559A JP S60257559 A JPS60257559 A JP S60257559A JP 59114202 A JP59114202 A JP 59114202A JP 11420284 A JP11420284 A JP 11420284A JP S60257559 A JPS60257559 A JP S60257559A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- integrated circuit
- circuit device
- well
- potential
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
- H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
- H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
- H10D84/85—Complementary IGFETs, e.g. CMOS
- H10D84/858—Complementary IGFETs, e.g. CMOS comprising a P-type well but not an N-type well
Landscapes
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】 〔技術分野〕 本発明はＣＭ（５８集積回路装置の構造に関する。[Detailed description of the invention] 〔Technical field〕 The present invention relates to the structure of a CM (58 integrated circuit device).
第１図は０ＭＯ８回路の基本構造を示す断面図であり、
１はＮ−基板、２はＰウェル領域、３はＮ型イオンを打
込んで作成したＮチャンネルトランジスタのソースおよ
びドｉ／イン、４はＰウェル領域２の１個所以上にＰ型
イオンを打込んで作成した一領域である。通常このＰ＋
領域４はω山配線により接続されて接地電位に保持され
る。FIG. 1 is a sectional view showing the basic structure of the 0MO8 circuit.
1 is an N-substrate, 2 is a P-well region, 3 is the source and doin of an N-channel transistor created by implanting N-type ions, and 4 is P-type ion implantation into one or more places in the P-well region 2. This is an area that has been created with a lot of effort. Usually this P+
Region 4 is connected by the ω-mount wiring and held at ground potential.
しかしながら近年、人工衛星塔載等により放射線の影響
を受けると酸化膜中に正の電荷が発生して蓄積され、Ｎ
チャンネルトランジスタの青の低下となって現われる。However, in recent years, when the oxide film is affected by radiation due to mounting on artificial satellites, positive charges are generated and accumulated in the oxide film, and N
This appears as a decrease in the blue color of the channel transistor.
また酸化膜が厚くなるとこの影響はさらに大きくなり、
ＶＴ２の低下という問題か生じる。Furthermore, as the oxide film becomes thicker, this effect becomes even greater.
This may cause a problem of a decrease in VT2.
本発明？、寸上記従来例の点に鑑み提案されたものであ
り、Ｐ−基板あるいはＰウェルの電位を負にすることに
より、放射線の影響を受けてディプレッション状態に近
くなっているＮチャンネルトランジスタのｖｙおよびＶ
Ｔｔの値を大きくしたＣｔＭＯ８型集積回路装置の提供
を目的とする。Invention? This was proposed in view of the above-mentioned conventional example, and by making the potential of the P-substrate or P-well negative, the vy and V
The object of the present invention is to provide a CtMO8 type integrated circuit device with a large Tt value.
本発明の構成はＰ−基板あるいはＰウェルが負電位に設
定されていることを特徴とする。The structure of the present invention is characterized in that the P-substrate or P-well is set to a negative potential.
以下図面を参照して本発明の詳細な説明する。 The present invention will be described in detail below with reference to the drawings.
第２図は本発明の実施例に係るＣＭＯ８基本回路の構成
を示す断面図であり、第１図と同じ番号は同じものを示
している。９はＰウェル基板に負電位を与える電源であ
り、Ｐ領域４に接続されている。FIG. 2 is a sectional view showing the configuration of a CMO8 basic circuit according to an embodiment of the present invention, and the same numbers as in FIG. 1 indicate the same elements. 9 is a power supply that applies a negative potential to the P well substrate, and is connected to the P region 4.
次に本発明の動作について説明する。Next, the operation of the present invention will be explained.
ＮチャンネルＭＯ８ＦＦｉＴのＶＴは、簡単に近似する
と ＶＴ雨Ｋ】σηコ’Ｂ８−更Ｑｓｓ という様に表
わさε０χ
れ’ ＶＢＳとＶＴの関係を図示すると第３図のように
なる。ここで、Ｋ１はゲート官化膜の厚さｔｏχ、酸化
膜の誘電率ε０χによって定まる定数、φＦは半導体の
フェルミレベル、 ＶＢＳはパックバイアス１ｌＥＥＥ
。The VT of the N-channel MO8FFiT can be easily approximated as follows. Here, K1 is a constant determined by the thickness toχ of the gate functionalization film and the dielectric constant ε0χ of the oxide film, φF is the Fermi level of the semiconductor, and VBS is the pack bias 11EEE.
.
Ｑｓｓはゲート酸化膜中やゲート酸化膜と半導体との界
面に存在する表面準位等である。この式から容易にわか
るように放射線の影響によりＱｓｓが増すとＶＴは小さ
くなるか電源９によりバックバイアス電圧ＶＩ１８を印
加するとｖＴは大きくなる方向に動く。即ち、ＱｓＩ３
によ、ってＶＴか低下した分はＶＢＳを４１１ 印加す
ることにより補償できるので、ａｂｆｏｓ回路ｔ。Qss is a surface level existing in the gate oxide film or at the interface between the gate oxide film and the semiconductor. As can be easily seen from this equation, when Qss increases due to the influence of radiation, VT decreases, or when back bias voltage VI18 is applied from the power supply 9, vT moves in the direction of increasing. That is, QsI3
Therefore, the decrease in VT can be compensated for by applying VBS of 411, so the abfos circuit t.
の安定した動作が可能となる。This enables stable operation.
この場合、Ｐ＋領域を通して与えるＰウェＡ／４の負の
電位は、外部から与えるものであってもよく、また第４
図に示すような負電位発生回路を内蔵し、その出力をＰ
ウェル電位として与えるものであってもよい。In this case, the negative potential of P wafer A/4 applied through the P+ region may be applied from outside, or
It has a built-in negative potential generation circuit as shown in the figure, and its output is P
It may be given as a well potential.
尚、本実施例ではＮ−基板、Ｐウェル構造の場合を説明
したが、第５図のようにＰ−基板のウェル構造の場合に
は、Ｐ−基板１０の電位を負にすることにより同様の効
果が得られる。In this embodiment, the case of an N-substrate, P-well structure has been explained, but in the case of a P-substrate well structure as shown in FIG. The effect of this can be obtained.
本発明は以上説明したように、ＣＭ５Ｓ集積回路装置に
おいてＰ−基板あるいはＰウニ／Ｉ／電位を負にするこ
とにより、放射線照射を受けた際の動作をより安定化す
る効果がある。As described above, the present invention has the effect of further stabilizing the operation when exposed to radiation by making the P-substrate or P-substrate or P-substrate/I/potential negative in a CM5S integrated circuit device.
第１図は従来例に係る従来例に係る０ＭＯ８回路の基本
構造を示す断面図、第２図は本発明の実施例に係るＣＭ
ＯＳ基本回路の構成を示す断面図、第３図はバックバイ
アス電圧ＶＢ８と物の関係を示す図、第４図は本発明の
実施例に係るＣＭＯＳ集積回路に内蔵された負電位発生
回路の回路構成図、第５図はＰ−基板Ｎウェル構造の本
発明の別の実施例に係るＣＭＯＳ基本回路の構成を示す
断面図である。
１・・・Ｎ型基板 ２・・・Ｐウェル領域３・・−Ｎチ
ャンネルトランジスタのソース、ドレイン
４・・・Ｐウェルの電位をとる拡散層
５・１・酸化Ｍ ｅ−・ゲートポリシリコニ７−・・Ｐ
チャンネルトランジスタのソース、ドレイン
８・・・Ｎ型基板の電位をとる拡散層
９・・・負電圧供給電源
１０・・−Ｐ型基板 １１・・・Ｎウェル領域１４・・
・Ｐ型基板の電位をとる拡散層１５・・・Ｎウェル電位
をとる拡散層
１６・・・負電位発生回路出力
第１圓
Ｍ２図
第３図
第４図
第５図FIG. 1 is a sectional view showing the basic structure of an 0MO8 circuit according to a conventional example, and FIG. 2 is a CM according to an embodiment of the present invention.
FIG. 3 is a cross-sectional view showing the configuration of the basic OS circuit. FIG. 3 is a diagram showing the relationship between back bias voltage VB8 and objects. FIG. 4 is a circuit diagram of a negative potential generation circuit built into a CMOS integrated circuit according to an embodiment of the present invention. FIG. 5 is a sectional view showing the structure of a CMOS basic circuit according to another embodiment of the present invention having a P-substrate N-well structure. 1...N-type substrate 2...P-well region 3...-Source, drain of N-channel transistor 4...Diffusion layer 5 that takes the potential of P-well 1.Oxidized Me--Gate polysilicon 7-...P
Source and drain of channel transistor 8...Diffusion layer 9 that takes the potential of N-type substrate...Negative voltage supply power source 10...-P-type substrate 11...N well region 14...
・Diffusion layer 15 that takes the potential of the P-type substrate...Diffusion layer 16 that takes the N-well potential...Negative potential generation circuit output 1st circle M2 Fig. 3 Fig. 4 Fig. 5
Claims (2)
ことを特徴とするｃＭｏｓ集積回路装置。(1) A cMOS integrated circuit device characterized in that a P-substrate or a P-well is set to a negative potential.
した負電位発生回路の出力に接続されることにより行わ
れるものであることを特徴とする特許請求の範囲第１項
に記載のｃＩＶ４ｏｓ集積回路装置。(2) The cIV4os according to claim 1, wherein the negative potential of the P-substrate or P-well is set by being connected to the output of a built-in negative potential generation circuit. Integrated circuit device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59114202A JPS60257559A (en) | 1984-06-04 | 1984-06-04 | CMOS integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59114202A JPS60257559A (en) | 1984-06-04 | 1984-06-04 | CMOS integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60257559A true JPS60257559A (en) | 1985-12-19 |
Family
ID=14631760
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59114202A Pending JPS60257559A (en) | 1984-06-04 | 1984-06-04 | CMOS integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60257559A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02196469A (en) * | 1989-01-25 | 1990-08-03 | Fujitsu Ltd | Semiconductor device |
| JPH06177335A (en) * | 1992-12-07 | 1994-06-24 | Nippon Steel Corp | I/o circuit of integrated circuit |
| US7180150B2 (en) * | 2003-12-31 | 2007-02-20 | Dongbu Electronics Co., Ltd. | CMOS image sensor and method for detecting color sensitivity thereof |
-
1984
- 1984-06-04 JP JP59114202A patent/JPS60257559A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02196469A (en) * | 1989-01-25 | 1990-08-03 | Fujitsu Ltd | Semiconductor device |
| JPH06177335A (en) * | 1992-12-07 | 1994-06-24 | Nippon Steel Corp | I/o circuit of integrated circuit |
| US7180150B2 (en) * | 2003-12-31 | 2007-02-20 | Dongbu Electronics Co., Ltd. | CMOS image sensor and method for detecting color sensitivity thereof |
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