JPS60257565A - Charge transfer device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] (Industrial application field) The present invention relates to a charge transfer device.

(Conventional Structure and Problems Therein) As is well known, charge transfer devices using MO8 integrated circuits are used in delay lines, filters, solid-state imaging devices, and the like. In recent years, with the advancement of LSI technology, charge transfer devices have also been mass-produced, and have become available at low cost and easy to use.

Here, a solid-state imaging device, which is one type of charge transfer device, will be explained as an example. Most solid-state imaging devices have a basic configuration in which a large number of photodiodes are arranged as photoelectric conversion means, and the optical signals stored in the photodiodes are read out by a charge transfer device.The photodiodes and the charge transfer section are mounted on the same semiconductor substrate. built into the top.

A conventional example of an n-channel charge transfer type -dimensional solid-state imaging device will be described with reference to FIGS. 1 and 2. FIG. 1 is a plan view of a conventional example. In FIG. 1, numeral 1 is a photoelectric conversion element having a photoelectric conversion and signal storage function for optical input information, and is usually a diffusion region 1 for forming a photodiode. Reference numeral 2 denotes a □ field section which sets the potential of the photoelectric conversion element section by .phi.1. 4 is a signal charge transfer section,
Reference numeral 3 denotes a shift gate section that controls the time at which the signal charge of the photoelectric conversion element section 1 is transferred to the signal transfer section 4 using a voltage φ8. The shaded region 5 is a channel blocking region, which is formed of a p-diffusion layer.

The solid-state imaging device shown in the figure is a two-layer polysilicon, buried channel type with two-phase locking operation, and the image signal is the first one.
Phase clock pulse φ1, second phase clock pulse φ
2, charges are transferred and φ1=φ2 is established.

FIG. 2(a) is a cross-sectional view taken along the line X-X in FIG. By forming this, an embedded mode operation is achieved. Note that the semiconductor substrate 7 is a p-type silicon substrate. FIG. 2(b) is a potential diagram when the optical signal accumulated charges are transferred (shifted) to the signal charge transfer section. FIG. 2(c) is a potential diagram when the signal charge accumulation operation by light is performed in the photoelectric conversion element section 1 simultaneously with the charge transfer operation of the signal charge transfer section 4. FIG.

The operation will be described below with reference to FIGS. 1 and 2 (,) to (C). When light is input to the photoelectric conversion element section 1 for a certain period of time, a signal is accumulated in the lower part of the photoelectric conversion element section 1 as shown in FIG. When the shift gate 3 becomes ``open'', the potential inside the substrate becomes as shown in FIG. 2(b), and at this time, the potential under the photoelectric conversion element J is It is set by the voltage φ applied to. When such a potential state is established, the accumulated signal charges are transferred to the signal charge transfer section 4. Next, the shift gate applied voltage φ.

returns to the low level ++LII, and the accumulated charge is transferred within the signal charge transfer unit 4 by the clock pulses φ1 and φ2 applied to the signal charge transfer unit 4, and is sent to an output detector (not shown). Ru. At this time, the shift game
At the same time that the applied voltage φ8 reaches °°L''', signal charges begin to accumulate in the photoelectric conversion element section 1.Similarly, following this operation, the accumulated charges from all the photoelectric conversion element sections are transferred to the signal charge. The signal charges are transferred to the unit 4 and sent to the output detector.The signal charges sent out in this way can be taken out as a time-series signal.

However, in the solid-state imaging device having the above configuration, in order to prevent the signals of each pixel from being mixed, it is necessary to start the next scan after reading out the signals of all pixels. Therefore, for example, even if it is determined from the information prior to reading a certain pixel that that pixel information is unnecessary, all pixels must be read out, which wastes time and is disadvantageous for high-speed scanning. . - (Objective of the Invention) The present invention has been made in view of the above drawbacks, and provides a charge transfer device that can instantaneously clear the signal of the signal charge transfer section.

(Structure of the Invention) In order to achieve this object, the charge transfer device of the present invention includes:
The signal charge transfer section includes a common control dart region and a drain region for discarding unnecessary charges, and the common control dart electrode and the gate electrode of the signal charge transfer section are formed of the same metal layer.

With this configuration, when all of the charges accumulated in the charge transfer section are unnecessary at a certain time, the control key is
By opening the gate, the unnecessary charge can be instantly discarded to the drain, and it can be manufactured using the same process as conventional methods.

(Description of Examples) Hereinafter, a solid-state imaging device using the charge transfer device of the present invention will be described in detail as an example with reference to the drawings.

FIG. 3 is a plan view showing a charge transfer type one-dimensional solid-state imaging device according to an embodiment of the present invention. As shown in the figure, the structure and arrangement of the photoelectric conversion element section 1, photogate section 2, shift gate section 3, and channel blocking region 5 are the same as those of the prior art. However, the shift key
The structure between the charge transfer section 3 and the signal charge transfer section 4 is greatly different from the conventional one. That is, in the present invention, the first dart electrodes 4-A of each stage of the signal charge transfer section 4 are connected to a common control case.
It is connected to a drain region 9 via a gate electrode 8 . In the layout shown in FIG. 3, the first dirt electrode 4-A and the photogate section 2 are the same metal film layer, and the second dirt electrode 4-B
The control dart electrode 8 and shift gate portion 3 common to the above can be formed of separate metal films of the same layer.

That is, it can be seen that it can be manufactured using the same process as the conventional method.

FIG. 4(a) is a cross-sectional view taken along the Y-Y line in FIG. It is a potential diagram. FIG. 4(C) shows when the control dart electrode 8 is open.
That is, it is a potential diagram when all charges accumulated in the signal charge transfer section 4 are discarded to the drain region 9. At this time, the applied voltage φ].

φ2. φ8. φ is the same as before, drain voltage φ
ゎ is set to a sufficiently high potential.

Next, the operation of this embodiment will be explained in Figs. 3 and 4 (a) to (c).
) will be used to explain in detail. In FIG. 3, when the voltage φ8 applied to the control gate electrode 8 is at a low level "L", the device operates in the same manner as the conventional example. At this time, in FIG. 4(b), in order to prevent the transferred charges from flowing to the drain region 9, the potential under the control gate electrode 8 is applied to the dirt electrode 4-A of the signal charge transfer section 4. It must be higher than the potential when the voltage φ1 is at the low level "L". For this purpose, either the +L77 level voltage of φ is made lower than the ``L'' level voltage of φ1, or the impurity concentration of the n-buried diffusion portion 6' under the control date electrode 8 is lowered to accommodate the signal charge. The impurity concentration needs to be lower than the impurity concentration of the n-buried diffusion section 6 below the transfer section 4.

Next, the pixel information is sequentially read out, and when all pixel information after a certain pixel is unnecessary, the voltage φ applied to the control gate electrode 8 is set to a high level (H), as shown in FIG. ″′
Then, all the charges accumulated in the signal charge transfer section 4 are discarded to the drain region via the control dart, and the signal charge transfer section 4 has no charge at all, and the next scan is started.

In addition, when the signal component due to the next scan is also unnecessary, if the soft gate voltage φ8 and the control gate voltage φ8 are also set to a high level state, unnecessary signals can be continuously discarded.

Another embodiment of the present invention is shown in FIG. 5, but since its operation is the same as that of the embodiment shown in FIG. 3, detailed explanation will be omitted.

As described above, according to this embodiment, when a 512-pixel image sensor is used as a 400-pixel element, in the conventional example, information on 401 to 512 pixels is also read out,
Only the 00 pixel is used, and additional time is required to read the 401 to 512 pixels. However, in this embodiment, this unnecessary pixel information can be instantly discarded, allowing high-speed scanning and saving time. can be used. Fortunately, when information from before a certain time is unnecessary, only valid information can be extracted by freely controlling the control gate voltage.

Furthermore, the accumulation time (period of shift clock φ8)
When the signal charge is long, the dark signal charge generated in the signal charge transfer section can be cleared by opening the control dart just before the application of the shift gate nozzle φ8. As described above, the present invention has various features.9.One gate electrode]
This is a simple configuration that adds two drain regions, and can be said to be very useful.

Although this embodiment has been explained using a buried channel type charge transfer type solid-state image pickup device with an n-channel two-layer polysilicon two-phase clock operation as an example, it can be applied to any device having a charge transfer function. not.

(Effects of the Invention) As described above, the charge transfer device of the present invention instantly clears the signal of the signal charge transfer section by providing a common control gate region and a drain region in the signal charge transfer section. can do.

Indeed, it can be fabricated using the same process as conventional ones, that is, the manufacturing process of two-layer silicon-buried channel charge transfer devices, and its practical effects are tremendous.

[Brief explanation of the drawing]

FIG. 1 is a plan view of main parts of a conventional charge transfer type -dimensional solid-state imaging device, and FIG. 2(a) is a sectional view taken along line XX in FIG.
Figures (b) and (c) are diagrams showing potential states corresponding to Figure 2 (a), and Figure 3 is a plan view of essential parts of a charge transfer type -dimensional solid-state imaging device according to an embodiment of the present invention. , Figure 4(a)
are YY cross-sectional views of FIGS. 3 and 5, FIG. 4(b), (
FIG. 5 is a plan view of a charge transfer type one-dimensional solid-state imaging device of another embodiment. 1... Photoelectric conversion element part, 2... Photocase part,
3... Shift gate section, 4... Signal charge transfer section, 4
-A...First dart electrode of signal charge transfer section, 4-B.
... Second dart electrode of signal charge transfer section, 5... Channel blocking region, 6, 6'... Buried diffusion section, 7... Semiconductor substrate, 8... Control dart electrode, 9... - Drain area. Figure 1 Figure 2 c Figure 3 Figure 4 Figure 5

Claims (1)

[Claims] on a semiconductor substrate, comprising a plurality of stages of signal charge transfer sections, a control gate region common to some or all of the stages of the signal charge transfer sections, and a drain/region for discarding unnecessary signal charges;
A charge transfer device characterized in that the gate electrode of the common control gate region is made of the same metal layer as the gate electrode of the signal charge transfer section.