JPS6025850A - Speed checking device for automatic train stop - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a speed checking device for a variable frequency automatic train stopping device, and in particular, a receiving antenna for receiving information from an on-board device and a speed check device for an on-board device. The present invention relates to a speed checking device in which a plurality of combinations with beacons that provide stop information are provided spaced apart in the direction of train movement.

PRIOR ART This type of speed checking device generally has the following structure, as shown in FIG.
Receiving antennas such as loop coils and resonant circuits (AI, A2
) and a ground element (C1°C2) such as a resonant circuit. Select, amplify, rectify, smooth and output 1! l! 1 to 1 by the circuit (6) and the output signal of this processing circuit (6)
A timer (7) that is triggered, a timer relay (TMR) that is operated by the output signal of this timer (7), a counter that counts the number of times this timer relay (TMR) operates by t1, and this A plurality of counter relays (CORo) are operated according to the h1 value of the counter (8).

COR+, COR2, COR3) and the contacts of the counter relay (COR[1,0OR2) (hereinafter, relay contacts are indicated by the same symbols as the corresponding relays, operating contacts are indicated by V-shaped marks, and falling contacts are indicated by V-shaped marks. a switching circuit (9) that switches the receiving antenna (AI, A2) connected to the input side of the processing circuit (6) using the inverted V-shaped mark (indicated by an inverted V-shaped mark); Equipped with a plurality of control relays (QR1, QR2) that turn on and off the above-mentioned ground coils (CI, C2) using contacts, and a set relay (STR) that sets a counter (8) according to external conditions, the onboard coil Only when the time from when it reaches the receiving antenna (A1, A2> to when it reaches the ground transducer (CI, C2) is longer than a predetermined time, the ground transducer (C1, C'2) is turned off and the onboard equipment side Stop information is not given.

However, in the conventional device of this type, the counter <8) is connected to a one-way relay (T) whose failure mode is as shown in FIG.
MR, CORo, COR+, C0R2, COR3, S
Since it is composed of T-type contacts, the device is complicated and expensive.

OBJECTS OF THE INVENTION The present invention provides an automated system with a simple structure that is more reliable than conventional devices in which the counter is configured with relay contacts, although it uses a semiconductor counter circuit known as a counter circuit. The purpose of the present invention is to provide a speed checking device for a train stopping device.

Structure of the Invention According to the present invention, a combination of a receiving antenna that receives information from an on-board device and a wayside element that provides stop information to the on-board device is spaced apart from each other in the traveling direction of the train. A timer relay is provided on the output side of a processing circuit that processes a signal received by the receiving antenna, the number of times the timer relay operates is counted by a counter, and the number of times the timer relay is operated is counted by a counter, and the ground terminal In a speed checking device for an automatic train stop device, in which the counter is turned on and off by the contacts of a control relay, the device is made compact by using a known semiconductor counter circuit, and it is also possible to A check circuit that outputs no output and a check relay that is operated by the output signal of this check circuit are further provided, and an operating contact of the check relay is provided in the energizing circuit of the control relay to detect the failure of the counter circuit when the counter circuit malfunctions. This is achieved by dropping all control relays to ensure Fehrleaf, thereby increasing reliability.

Example The present invention will be described below based on embodiments shown in the drawings.

In FIG. 1, (1) is a train equipped with an on-board device (2), which travels along a running path (3) from left to right in FIG.

As shown in Figure 2, the on-board device 2) includes an oscillator (1 (1)) that oscillates at a frequency fa, and is connected to this oscillator (10) as a feedback circuit and is installed at the head of the train (1). It has a processing circuit (12) that selects, amplifies, rectifies and smoothes the frequency fO, and a main relay (MR) that is operated by the output signal of the processing circuit (12). The operation contact of MR) is inserted into the brake command circuit 13).

The processing circuit (12) includes a bandpass filter (14) that conducts current at a frequency fO that is the output of the oscillator (10), an amplifier (15) that amplifies the output, and a rectification and smoothing circuit that rectifies and smoothes the output. I (76), and if a signal of frequency fO is not input, there will be no output, which causes the main relay (MR) to fall.

The brake command circuit (13) is connected to the main relay (
MR) has fallen, and a brake command is output to the effect that the brakes should be applied.

On the running path (3), there is a receiving antenna (A1) and a ground coil (C
1) and the reception anti-no (A2) and ground conductor (
C2) A total of two sets of which combinations are set. The receiving antenna (A1) and the ground coil (CI>) are installed with an interval of Ll in the direction of train (1).
2) and the beacon (C2) are installed at intervals of 12 in the direction of train movement.

As shown in FIG. 3, each receiving antenna (A1, A2> is a known circuit in which a capacitor and a load resistor are connected in parallel to a coil, and a transformer (201, 202>
connected to.

As shown in Fig. 3, each ground element (CI, C2') is a known circuit in which operating contacts of control relays (QRI, QR2), which will be described later, are provided in a resonant circuit in which a coil and a capacitor are connected in parallel. .

The verification circuit (4) calculates the time it takes for the onboard coil (11) of the train (1) to reach the ground coil (C1) from the receiving antenna (A1) and the time it takes for the onboard coil (11) of the train (1) to reach the ground coil (C2) from the receiving antenna (A2). It is determined whether or not each of the @ intervals is longer than a predetermined tfi interval, and when it is shorter than a predetermined tfi interval, the ground coil (C1, C2) is enabled and stop information is given to the on-board device.

As shown in FIG.
A processing circuit (21) which selects the component of the back frequency fO of the received signal, amplifies it, rectifies and smoothes it to obtain an output, and a timer (21) which is triggered by the output signal and outputs a signal for a predetermined period of time after a certain period of time. 22), a tine relay (TMR) operated by the output J signal of this timer, and a counter (
23) and a plurality of (three in the illustrated example) counter relays (COR) that are operated according to the count value of the counter (23).
O.

COR1, COR'2), a check circuit (24) for checking failures of the counter (23) and counter relays (CORO, CORI, COR2), and an output signal of the check circuit (24). A check relay (CKR) and a receiving antenna connected to the input side of the processing circuit (21) are connected to the counter 1. , l l/-(C
A switching circuit (25) that switches under the contact condition of OR (1,0OR+>) and the counter relay (CORI, COR2)
) Control relay (QR5) that controls the ground coils (C1, C2) individually according to the contact conditions of relay (CKR)
QR2) and a set relay (STR) for setting the counter (23).

The processing circuit (21) includes a bandpass filter (26) having a pass characteristic of frequency [0, an amplifier (27) that amplifies its output signal, and a rectification and smoothing circuit (28) that rectifies and smoothes the output signal. This is a known circuit having a switching circuit (
25) to the input terminal of a bandpass filter (26).

The timer (22) is triggered by the output signal of the processing circuit (21) and outputs a predetermined time signal after a predetermined time.

The counter (23) is a known circuit made of semiconductor, such as a diode or a transistor, and a counting signal is input to a signal input terminal via an operating contact of a timer relay (TMR>), A set signal is input to the set terminal via the operating contact of the set relay (STR).This counter (23)
If the timer relay (TMR) operates in this state, the count value will be "'".
1", the first output terminal (OUT+) becomes output, and then the timer relay (TMR> operates again, the value of B1 becomes "2" and the second output terminal C ((lIT
2) becomes output.

The counter relay (COR+) is operated by the signal from the first output terminal of the counter (23), and the counter relay (COR+) is operated by the signal from the first output terminal of the counter (23).
OR2) is operated by No. 15 of the second output terminal of the counter (23). In the illustrated example, the counter relay (CORo) is configured to be energized via the operating contacts of the cellar 1 to relays (Sl-R) and the falling contacts of each counter relay (COR+, COR2). Counter (23
) may also be operated by the output signal of the counter (23) when the divination value of 1 is other than "1" and "2".

Check circuit (211>1, each counter relay (CO
Signals for operating R11, COR1, COR2) are individually input to the input terminals, and if any one of the counter relays is operating, there will be an output.

The check relay (CK R) is connected to the output terminal of the check circuit (24) via a self-holding operating contact once the set switch is pressed down and operates.
Continues operation under normal conditions. Furthermore, when the counter (23) is not operating, it continues to operate due to the voltage applied through the falling contact of the set relay (STR).

The switching circuit (25) has an operating contact of the counter relay (COR[l) provided between the secondary coil of the transformer (20+) and the processing circuit (21), and an operating contact of the counter relay (CORI) provided between the transformer (20+) and the processing circuit (21). , 02) and the processing circuit (21).

The control relay (QRI) is energized through the operating contacts of the counter relay (COR1) and check relay (C, KR), and the control relay (OR2) is energized via the counter relay (COR1) and check relay (C, KR).
R2) and the check relay (at CKi) are energized through their operating contacts.

The set relay (STR) is energized and operates under conditions such as when the train (1) enters a closed section where the speed check device is installed or an area where the speed check device is installed. The vehicle will be cut off and fall due to a blocked section where the speed check device is installed or the vehicle advances from the area where the speed check device is installed.

Next, the operation of the above device will be explained with reference to FIG.

The oscillator (10) of the on-board device always oscillates at the frequency of fO, and therefore the main relay (MR) operates and does not output a brake command. In addition, the speed check device on the ground is activated when the start switch (SW) is closed while the set relay (STR) is down.
The C check relay (CKR) is energized via the falling contact of the relay (STR). In this state, each counter relay (CORo, COR+, , OR2) and each control relay (QR+, QR2) has fallen. Therefore,
The earth terminals (C1, C2) are now valid. In addition, the check circuit (24) is connected to either counter relay ((”
:ORO, COR+, COR2) are also not energized, so there is no signal, but the check relay (CKR) is energized via its own operating contact and the drop contact of the let relay (STR).

As train (1) progresses, when the set relay (STR) operates at time (tB), the counter relay (COR) operates.
O) is energized to the cellar 1 through the operation contact of the relay (STR) and the falling contacts of the counter relays (COR+, COR2). As a result, the switching circuit (25) connects the receiving antenna (A1) to the input side of the processing circuit (21), and the check circuit (24) has an output, so the check relay (CKR) does not operate. last.

As the train (1) progresses, when the onboard child (11) reaches the receiving antenna (A1) at time (t2), a signal of frequency fO is received by the receiving antenna (A1) and is sent to the processing circuit ( 21), the timer (22) is triggered and outputs a signal for a certain period of time, and as a result, the timer relay (TMR) operates for a certain period of time.

When the timer relay (TMR) operates, the counter (23
) becomes “1”, the counter relay (C
Since OR+) operates, the counter relay (CORO)
falls. Therefore, the check circuit (24) maintains the output state.

When the counter operates, the switching circuit (25) switches the receiving antenna (A2) from the receiving antenna (A1) to the processing circuit (
21).

Also, when the counter relay (CORI) operates, the control relay (QRI) operates, which causes the ground element (C1) to
is shorted and becomes invalid. Therefore, the time from the time when the onboard child (11) reaches the receiving antenna (A1) until the time when the onboard child (11) reaches the receiving antenna (C1) is the same as when the onboard child (11) reaches the receiving antenna (A1).
If the time (T2) from when A1) is reached until the control relay (QRI) is activated, the car's second device (2)
The oscillation frequency of the oscillator (10) changes to the resonance frequency (≠f) of the ground element (CI), and the main relay (MR)
falls and outputs a brake command. However, when the onboard coil (11) reaches the ground plate (C1) after the above-mentioned time (T1), the onboard MfFl (2) has the ground coil (CI) short-circuited, so the oscillator (10) is the frequency [oscillation continues at 0], the main relay (MR) continues to operate and does not output a brake command.

As the train (1) progresses, when the onboard child (11) reaches the receiving antenna (A2) at time (t3), a signal of frequency [0 is received by the receiving antenna (A2) and the processing circuit ( 21), the timer (22) is triggered again and outputs a fixed time signal after a fixed time (1-1), and as a result, the timer relay (TMR) operates again for a fixed time.

When the timer relay (TMR) operates, the counter (23
) becomes “2”, which causes the counter relay to
(COR2) is activated and the counter relay (COR+) is dropped, so the switching circuit (25) is switched to the receiving antenna (A2).
) is separated from the processing circuit (21).

In addition, the control relay (Qri) is a counter relay (COR).
I> falls and activates the ground element (C1), and the control relay (OR2) activates the counter relay (CO
When R2> is activated, it operates and disables the ground coil (C2). Therefore, the onboard child (11) is connected to the receiving antenna (
The time from when the onboard element (11) reaches the receiving antenna (A2) until the time when the onboard element (11) reaches the receiving antenna (A2) until the control ηU relay (OR2> operates) is 1"2), the on-board device (2) causes the main relay (MR) to fall and outputs a brake command in the same manner as described above, and after time (T2), the main relay (MR)
continues to operate and does not output a brake command.

When the set relay (STR) falls at time (t4), the second output terminal (0'UT2) of the counter (23) becomes non-output, so the counter relay (COR2) falls, thereby causing the control relay ( Q[and 2) falls and -C
Turn on Ji Doko (C2).

If the counter relay (COR'2> falls, the check circuit (24) will cause all counter relays (C0RO, CO
Since R3COR2) is in a de-energized state, there is no signal, but the check relay (CKR) is energized through its own operating contact and the drop contact of the set relay (STR), and continues to operate.

Next, one embodiment of the check circuit (24) shown in FIG. 5 will be described.

This check circuit (24) consists of a generator (30) for generating an alternating current signal of a constant frequency, a transistor (31) to which the alternating current signal is manually operated as a base, a transformer (32), and a transformer provided on the output side of the transformer. It includes a rectifier circuit (33) and a resistor <34.35) connected in series with each relay <coRa, CORI, 0012). The negative side of each counter relay (CORO, C0R1, COR2) is connected to the negative side power supply (-■) via the resistor (34, 35), and the check relay (CKR) is connected to the rectifier circuit (33).
connected to the output side of the The base of the transistor (31) is connected between the resistors (34) and (35), and is also connected to the alternating current signal generator (30).
The collector is connected to the positive power supply (→-■) via the primary coil of the transformer (32), and the ]-mitter is connected to the ground (OV
)It is connected to the.

In addition, counter L'-(CORO, CORI).

Instead of inputting the current flowing through the check circuit (24) to the counter relay (CORO, CORl,
Check the current directly through the contacts of the COR2) circuit (2
4) may be included.

In this check circuit (24), the transistor (
31) are all counter relays (CORO.

If COR+, COR2) are not energized, the base voltage will be biased by the negative side voltage m (-V) and will only change in the cutoff region as shown by the symbol (36) in Figure 6, so the on Since it remains as it is, there will be no AC output. Furthermore, when two or more counter relays are energized, the transistor (31) has a base voltage equal to the sum of the currents flowing through those counter relays, and is shown in FIG.
), it is greatly biased toward the positive side and changes in the saturation region, so there is no AC output. Therefore, in the check circuit (24), if all the counter relays of τ are not energized, the 1-transistor (31) remains in A, so there is no AC output, and if two or more counter relays are When energized, the transistor (31) remains on without any alternating current horn. but,
When one counter relay is energized, the base pressure of one hemi resistor (31) changes to sign (38) in Fig. 6.
), it changes in the active region, so it repeats on and off depending on the AC signal, and as a result, the AC signal is induced on the secondary side of the transformer (32), and the check circuit (24)
) will have output.

The present invention is applicable not only to a device using a resonant circuit consisting of a coil and a capacitor as a receiving antenna (AI, A2), but also to a device using a loop coil as a receiving antenna (AI'-, A2') as shown in FIG. It can also be applied to devices used as Further, the present invention can be applied not only to a device that checks the speed at two points, but also to a device that checks the speed at three or more points by increasing the number of stages of the counter (23). moreover,
As the check relay (24), other circuits may be used as long as they do not output when the counter (23) is out of order.

Effects of the Invention As described above, the present invention comprises a check circuit that provides an output only when only one of each counter 1N is operating, and a check relay that is operated by the output signal of this check circuit. Since the operating contact of the above-mentioned check I- is provided in the energizing circuit of the control relay, if the counter malfunctions, the control relay will not operate due to the check relay and the ground element will not be disabled, so that the -C above-mentioned counter It uses a known semiconductor circuit (and has extremely high reliability).

Furthermore, since a well-known half-nine circuit is used for counters, it is extremely easy to draw.

[Brief explanation of the drawing]

Fig. 1 is a diagram showing an example of an automatic train stopping device, Fig. 2 is an electric circuit diagram showing an embodiment of an on-board device, and Fig. 3 is an embodiment of a speed checking device according to the present invention. FIG. 4 is an electrical circuit diagram showing the operation of the same speed checking device; FIG. 5 is an electrical circuit diagram of an embodiment of the check circuit; FIG. 8 is a diagram showing another embodiment of the automatic train stopping device, and FIG. 8 is a diagram showing an example of a conventional speed check device. (21): Processing circuit, (22): Timer, (23)
: Counter, (24) : Check circuit, (25)
: Switching circuit, (A1.A1'): Receiving antenna, (A2, Δ2-): Receiving antenna, (CI): Ground element, (C2): Ground element, (QRI): Control relay, (OR2
): Control relay, (TMR): Timer relay, (CORO): Counter relay, (COR+): Counter relay, (COR2): Counter relay, (CKR): Check relay. Patent applicant Nippon Signal Co., Ltd.

Claims (1)

[Scope of Claims] 1) A plurality of combinations of receiving antennas for receiving information from on-board devices and ground wires for providing stop information to said on-board devices are provided spaced apart from each other in the direction of travel of the train, and A timer is installed on the output side of the processing circuit that processes the signal received by the antenna (), the number of times the timer operates is counted by H1 with a counter, and the ground element is turned on by the contact of the control relay according to the counted value of the counter.・The speed checking device of the automatic train control device that is set to turn off is equipped with a check circuit that uses a semiconductor counter circuit as the counter, and that outputs no output when the counter malfunctions. 1. A speed checking device for an automatic train control device, comprising: a check relay operated by an output signal of a check circuit; and an operating contact of the check relay is provided in an energizing circuit of the control relay.