JPS60263268A - Vector processor - Google Patents

Abstract

PURPOSE:To execute high speed processing of compressive conversion and simple control by providing a parallel vector register part having plural operand vector registers, result vector registers and mask data registers. CONSTITUTION:A parallel vector register part 1 has operand vector registers, result vector registers and mask data registers of four pieces each. Four vector elements read out in parallel from each operand vector register are supplied to an aligning circuit 2 through a data bus 1000. These vector elements are transferred in parallel through a data bus 2000, and written in parallel to each result vector register. Also, four mask elements read out in parallel from each mask data register are transferred in parallel to a compressive conversion controlling circuit 3 through a mask data read-out bus 1300. In such a way, the compressive conversion of a vector is executed in parallel, therefore, high speed processing and simplification of a control can be realized.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to data transfer control in a vector processing device, and particularly to vector compression conversion control thereof.

(Prior Art) In a conventional vector processing device, when reading vector elements from the operand vector register and processing them, each element is read out one by one in sequence, and when writing to the result vector register, each element is read out one by one in sequence. They were written one by one. In such a vector processing device, it is relatively easy to perform vector compression conversion.

Next, compression conversion will be explained. FIG. 1 is an explanatory diagram of compression conversion. A mask data register MSK that can store k (k: positive integer) mask elements, and an operand vector register OP that can store up to 2 elements of the same vector corresponding to each mask element.
Similarly, there is a result vector register R8L which can store up to two elements of the same vector corresponding to each mask element. Therefore, it is assumed that elements as shown in FIG. 1 are stored in the mask data register MSK and the operand vector register OPR, respectively. From this state, the elements of the operand vector register OPR corresponding to the ↑ 1' storage position of the mask element where -II is stored are sequentially written without disturbing their order.
Compression conversion is performed by storing it in the result vector register.

In the above-described compression conversion, it is desirable to process a plurality of vector elements in parallel at the same time in order to perform high-speed processing. However, in this case, the drawback is that the control is complicated.

(Object of the Invention) An object of the present invention is to eliminate the above-mentioned drawbacks by performing high-speed processing by compressing vectors in parallel using a relatively simple control means, and to easily perform control. The object of the present invention is to provide a vector processing device that is constructed in a simple manner.

(Structure of the Invention) A vector processing device according to the present invention includes operand vector 7972 means, result vector V register means, mask data register means, read data bus means,
Write data bus means.

The apparatus includes align circuit means, integration circuit means, encoder means, and decoder means, and is configured to perform vector compression conversion.

The operand vector register means is for reading out a plurality of vector elements belonging to the same vector during one cycle.

The result vector V-signuter means is for writing the plurality of vector elements belonging to the same vector during one cycle.

The mask data 7 signal bus means corresponds to each element of the operand vector register means and the result vector register means, and is used to read out the plurality of mask elements during one cycle. This is for reading out the plurality of vector elements from the vector register means.

The write data bus means is provided for writing the plurality of vector elements into the result vector register means.

The align circuit means is for selectively connecting the read data bus means and the write data bus means.

The accumulation circuit means is for accumulating the -1# number of mask elements read through the read data bus means.

The encoder means is for generating a write address increment signal for the salt vector register means by the summation value obtained from the summation circuit means and the mask element read out (above).

The decoder means is for generating a connection control signal to the align circuit means based on the mask element read out above and the integrated value. Explain.

FIG. 2 is a block diagram showing an embodiment of a vector processing device according to the present invention. In FIG. 2, the vector processing device includes a parallel vector register section 1.

Align circuit 2, compression conversion control circuit 6, read data bus 1000, write data/< bus 2000, and mask data read bus 1300! :.

It consists of a write address increment control signal line 6000 and an align circuit connection control signal line 6200.

FIG. 8 is a block diagram showing details of the parallel vector register section 1. In this example, there are four (generally n, n=1t2+8..., a positive integer, here n=4)
For example, the vector register section VE-0 is composed of a mask data register MSK-0, an operand vector register 0PR-0, and a result vector register R8L-0. ing. Generally, the vector register section vE-
1 (i=0, 1, 2, 8) is ff7 data register M
SK-i (i=0, 1, 2-8).

Operand vector register 0PR-i (1=o.

1.2.3) and result vector register R8? L
-i (i=o, 1t18). Here, operand vector register 0PR-i (i=o, 1, 2 .
8) and result vector register R8L-t(i
If you use a register that can be read/written as =o+1*2p8), the result vector V register R8L=
and operand vector register 0PR-i (i=o11
1218) can be configured with the same register.

Each operand vector register 0PR-0 to 0PR-8
The four vector elements read in parallel from
The data is supplied to the align circuit 2 via a read data bus 1000 for transferring vector elements in parallel. The vector elements supplied from the align circuit 2 via the write data bus 2000, which is used to transfer four vector elements in parallel, can be written in parallel to each of the result vector registers R8L-0 to R8L-8. 10 to M S in each mask data register M8
The four mask elements read out in parallel from K-8 are transferred in parallel to the compression conversion control circuit 3 via mask data readout nodes 1 and 00.

FIG. 4 is a block diagram showing the align circuit 2 in detail. In FIG. 4, the align circuit 2 includes four input ports 20-0 to 2 connected to the read data bus 1000.
0-3, four output ports 21-0 to 21-3 connected to the write data bus 2000, and a connection line 22 for connecting each input/output boat. The align circuit 2 is supplied with an align circuit connection control signal from the compression conversion control circuit 3 via a signal line 6200.

This signal is supplied to four input ports (21-0 to 21-3) corresponding to n=4, and the connection between each input/output port is controlled by this signal. For example, the information ωo=ω1=0 (ki 0,
0〃), ω2 = 1 ('Or1〃), ω3-2 (Ki 1, 0') is supplied via the signal line 6200, the way each boat is connected is as follows. It will look like this: Information ω. Output capo that is supplied with) 21-
0 and information ω1 are supplied) 21-1
corresponds to ω0 = ω1 = O, and both input boats 20−
Output port connected to 〇 and supplied with information ω-)2
1-2 is connected to the input boat 20-1 in response to ω2=1, and the output port 21-8 to which information ω3 is supplied is connected to the input port 20-2 in response to ω3=2. .

FIG. 5 is a block diagram showing details of the compression conversion control circuit 6. In FIG. 5, the compression conversion control circuit 6 includes a 4-bit mask register 61 connected to a mask data readout bus 1600, an adder 621, and a register 62.
2, an integrating circuit 62, an encoder 66, and a decoder 641.

It consists of a shifter 642. The encoder 36 inputs the output of the mask register 61 and the integrated value Register R8L-0 to R8L-8
Control the write address of each trail. Mask data is input to the decoder 641, and the output of the decoder 641 is sent out on the align circuit connection control signal line 6200 as information ω0 to ω3 for each 2 pins, and the align circuit 2
is supplied to.

Next, the operation of this embodiment will be explained in detail.

First, it is assumed that each register of the parallel vector register unit 1 is initialized as follows.

That is, each mask data register MSK-0 to MSK
-1 is set to a specific mask data value. The order of settings is determined, for example, as follows. That is,
The mask data is 10110100 as shown in Figure 1.
..., the first one 1 of the mask data is set to the first address of the mask data register MSK-0, and the mask data register MSK-0 is set to the first address of the mask data register MSK-0.
The next mask data 0 is set at the first address of K-1, and the mask data register MSK-
The fourth mask data 1 is set at the first address of 8. Thus, the first address of each mask data register MSK-0 to MSK-8 of the parallel vector register section 1 contains mask data 101 as shown in FIG.
1 # is set and mask data '01' is placed in the next address.
00' is set, and thereafter each mask data is set in each mask data register MSK-0 to MSK-8 in the same manner.

Next, suppose that each element of the operand vector is Aor A1 + A2 as shown in FIG. 1. In this case, as shown in FIG. 8, the first element of the operand vector register 0PR-0 is The vector element AO is set to the address, the next vector element A1 is set to the first address of the operand vector register OP R-1, and the vector element A3 is set to the first address of the operand vector register 0PR-8 in the same manner. Set. In this way, each operand vector register 0PR-0 to 0 of the parallel vector register section 1
The first address of PR-8 is the vector element Ao.
+A1 *Az +As are set respectively. Similarly, operand vector register 0PR-0~0P
The next address of R-8 is vector element A4 e
As r Aa r At are set respectively, and in the same manner, vector elements of all operand vectors are stored in each operand vector register 0PR-0 to 0.
PR-8Kl [Next setting.

Result registers R8L-0 to R8L-8 are stored in sioperand vector registers 0PR-0 to 0PR by compression conversion.
-8 vector enement Ao+AI r AS ・・
・ is written compressed, so there is no need to make initial settings. Therefore, the result vector registers R8L-0 to R8L-8 shown in FIG. 3 are set not with the initial values as described above, but with vector elements after compression conversion as will be explained later.

Compression conversion starts with the above initial settings, but in the 0th cycle of compression conversion, the mask data stored in the first address of the mask data registers MSK-0 to MSK-8 of parallel vector register section 1 '1[1
1” are read in parallel and the mask data read bus 130
The signal is stored in the masked register 1 of the compression conversion control circuit 6 via the bit 0.

At this time, each operand register 0PR-0 to 0PR-
Each vector element Aor At pA2 of the operand vector stored at the first address of 8.
As is read and output to input ports 20-0 to 20-8 of align circuit 2 via read data bus 1000. Decoder from the mask data stored in the mask register 61! +41 generates an align circuit connection control signal, supplies this to the align circuit 2, and connects the input ports 20-0 to 20-3 of the align circuit 2 and the output ports 21-0 to 21-8. control. This control is performed as follows.

6 and 7 are diagrams showing a circuit configuration diagram and logical values of the encoder 66 shown in FIG. 5, respectively. The output of the encoder 36 is the result vector register R8L-
0 to RS L -80 is supplied to the parallel vector register unit 1 as a step controller. The logical value shown in Figure 7 is n
= 4, but a similar encoder can be easily constructed even when n-f-4 by setting the logical values as follows. That is, the input mask data mQ-mn1 is added to the heel addition value m(1 to mn-1, and the number of qi1N included in a(,
Assign 1# from the Ω side to the left, and all the remaining numbers are I't.
As □I, the result is cyclically shifted to the right by the integrated value X (write rotation). The step control signals of the result vector registers R8L-0 to R8L'-8 obtained in this way are based on the mask data m(, -ml is LS l
#, % Q #%SI 11. %l#, and when the accumulated value At this time, since the vector element of the result vector has been transferred to that vector section, only the vector element Aor A2 r A3 is written to the first address of the result vector register R8L-0 to RST, -2. It will remain. However, the write address of result vector register R8L-3 is not incremented;
vector element A as data to be transferred to
3 is written to the first register of result vector register R8L-8, but it will be rewritten in the next cycle. Therefore, as shown in FIG. 8, the first addresses of the result vector registers R8L-0 to R8L-2 contain vector elements Ao, As, and A.
s is stored.

In the first cycle, the vector element A4 + As p Am r AT of the next address is read from each operand vector register 0PR-0 to 0PR-8, and is input to the input ports 20-0 to 20-8 of the align circuit 2. Ru. In this case, the mask data register MS
Similarly, the next data from K-0 to MSK-8 is % 0
100# is read and stored in mask register 61. In the register 622 of the integration circuit 62, the previous integration value As a result, A7 v A7 # AT +AB is output to the output ports 21-0 to 21-8 of the align circuit 2, respectively. On the other hand, since the output of encoder 3 is %Q0011, vector element A5 is written only to result vector register RS L -8, and then the write address is incremented. At this time, vector element A7*At+A7 is written to the other result vector registers R8L-0 to R8L-2, but since the address is not incremented, it will be rewritten in the next cycle.

FIG. 8 is a diagram showing information generated by the decoder 641 shown in FIG. 5. In FIG. 8, the portion indicated by X is a connection that is not used in the compression/conversion operation, so it may be set so as to be easily configured in hardware. In the above explanation, the connection information of electric 0〃 is assigned corresponding to m.
When the connection information of -1 was assigned to ml, the connection information of 2 was assigned to m2, and the connection information of 3 was assigned to ml, the mask bit mQ t ITII HIn2 r l'nl'
The above connection logic is such that the connection information such as I' is arranged side by side from the left side and cyclically shifted to the right in accordance with the integrated value.

FIG. 9 is a circuit diagram showing an example of the configuration of the decoder 41.
QIll in FIG. 9 indicates that a constant '1' is output. Here, the logical values shown in FIG. 8 are realized by the circuit configuration shown in FIG. FIG. 9 shows an embodiment in which n=4, and the structure can be easily constructed even in the case where n≠4.

For example, when n = 2, -Ol is assigned as the connection information corresponding to ml, N1N is assigned as the connection information corresponding to ml, and the mask bit mQ and the contents of ml become %l.
By arranging connection information such as 1 from the left, connection information of the align circuit 2 can be obtained so that compression conversion can be performed.

For example, when n=5, %OI is similarly assigned as the connection information corresponding to mQ, turtle]l is assigned as the connection information corresponding to ml, and 2 is assigned as the connection information corresponding to m2.
Decoder 64 that can perform compression conversion by allocating %N as connection information corresponding to ml, and %4〃 as connection information corresponding to m4 and performing the same operation.
1 logic is obtained.

In FIG. 8, the output signal of the shifter 342 corresponding to the integrated value Shift (Light Rotate)
It's something new. As a result, when the mask data '1011' is stored in the task register 31,
Since the integrated value is X-0, the output of the decoder 641 is ωo
-0. ω1=2. Since ω2=8 and ω3=3, the decoder 341 supplies -0288' to the align circuit 2. As a result, each input port 20 of the align circuit 2
-0 to 20-3 and each output boat 21-0 to 21-3 are connected as described above.
As a result, the vector elements)Ao, A:;, Aa+A3 are output as data to the write data bus 2000 connected to the write data bus 2000 connected to the write data bus 2000 connected to the write data bus 2000 connected to the write data bus 2000 connected to the write data bus 2000 connected to the write data bus 2000 connected to the write data bus 2000 connected to the write data bus 2000 connected to the write data bus 2000 connected to the write data bus 2000 connected to the write data bus 2000 connected to the write data bus 2000.

By repeating the above cycle one after another, the compression conversion shown in FIG. 1 can be executed correctly.

In this embodiment, the number (n) of data to be processed in parallel is mainly four, but this is just one example, and the present invention is not limited to this example.

As described above, when the present invention is adopted, the control signals supplied to the align circuit and parallel vector register section for efficiently compressing and converting vector data can be controlled by a compression conversion control circuit with a relatively simple hardware configuration. Can be generated.

(Effects of the Invention) As explained above, the present invention has the advantage that efficient compression conversion can be performed by providing and controlling a plurality of operand vector registers and a plurality of result vector registers. There is.

[Brief explanation of drawings]

FIG. 1 is an explanatory diagram for explaining compression conversion of vector elements. FIG. 2 is a block diagram showing an embodiment of a vector processing device according to the present invention. FIG. 8 is a block diagram showing details of the parallel vector register section shown in FIG. 2. FIG. 4 is a block diagram showing details of the align circuit shown in FIG. 2. FIG. 5 is a block diagram showing details of the compression conversion control circuit shown in FIG. 2. FIG. 6 is a circuit diagram showing details of the encoder shown in FIG. 5. FIG. 7 is a diagram showing data obtained by using the encoder shown in FIGS. 5 and 6. FIG. 8 is a diagram showing information obtained by the decoder shown in FIG. 5. FIG. 9 is a circuit diagram showing an example of a circuit configuration of a decoder for realizing the information shown in FIG. 8. 1... Parallel vector register section 2... Align circuit 6... Compression conversion control circuit 20-0 to 20-3... Input port 21-0 to 21-3... Output port 31... Mask register 62... Product X circuit 66... Encoder 641... Decoder 342... Register 621... Adder VE-0 to VE-8... To vector register section M8
0-M5K-, l...Mask data register 0PR-0 to 0PR-1... Operand vector register T? , 5L-0 to R8L-3... Result vector register 22.1000.1300, 20()0. Ro000゜6
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Claims (1)

[Claims] Operand vector 7972 for reading multiple vector elements belonging to the same vector in one cycle
means, result vector register means for writing the plurality of vector elements belonging to the same vector during one cycle, corresponding to each element of the operand vector register means and the result vector register means, mask data register means for reading said plurality of mask elements during a cycle; read data bus means for reading said plurality of vector elements from said operand vector register means; and said result vector register means. write data bus means for writing said plurality of vector elements to said plurality of vector elements; align circuit means for selectively connecting said read data bus means and said write data bus means; an accumulation circuit means for accumulating -11 of the mask elements that have been read, and a write address for the result vector register means based on the accumulation value obtained from the accumulation circuit means and the read mask element; Vector compression conversion is performed by comprising an encoder means for generating a step signal and a decoder means for generating a connection control signal to the align circuit means based on the read mask element and the integrated value. A vector processing device characterized by being configured as follows.