JPS60263272A - Two-dimensional vision recognizing device - Google Patents

Abstract

PURPOSE:To eliminate noise contained in a binary-coding signal in case of generating a pattern, to improve an object recognition accuracy, and also to execute processing at a high speed by providing a noise eliminating means and a signal restoring means. CONSTITUTION:A noise eliminating part 31 of a noise eliminating circuit 30 is constituted of shift registers 33, 34 and an AND circuit 35. The register 33 outputs a delay output B by delaying a binary-coding signal A containing a noise portion by the timing of a clock signal CK, and the register 34 outputs a delay output C by delaying the output B by another one picture element portion. In the AND circuit 35, AND D of both these outputs B, C is executed and in that case, a noise portion is eliminated. Also, a signal restoring part 32 is constituted of a shift register 36 for outputting a delay output I by delaying the AND output D by one picture element portion, and an OR circuit 37 for obtaining OR of the output D and the output I, and a pattern signal is restored by the output J of the circuit 35. Since the noise is eliminated in such a way, the object recognition accuracy can be improved, and also the processing can be executed at a high speed.

Description

[Detailed Description of the Invention] <Technical Field of the Invention> The present invention involves converting an image of an object to be recognized into black and white binarization to determine an input cover pattern, and comparing this input cover pattern with a standard pattern to recognize the object to be recognized. Related to two-dimensional visual recognition device,
In particular, the present invention is particularly useful when inserting cover patterns or standard patterns.
A new noise removal method for removing noise contained in a binary signal is provided.

<Background of the Invention> In general, a two-dimensional visual recognition device recognizes an object by superimposing an input A-turn and a standard pattern on an image, detecting the degree of superimposition and coincidence of both/N6 turns. . Therefore, if noise is included in the input/f-turn, etc., this will have a subtle influence on the determination of whether the turns match in both directions, causing a reduction in recognition accuracy. In addition, when comparing 7N6 patterns, when detecting the amount of positional deviation between both patterns and correcting the positional deviation, incorrect positioning may occur if noise is mistakenly recognized as part of the pattern. In such a case, object recognition becomes impossible.

<Object of the Invention> An object of the present invention is to provide a two-dimensional visual recognition device that improves object recognition accuracy by removing noise contained in a binarized signal when generating a pattern.

<Structure and Effects of the Invention> In order to achieve the above object, the present invention includes a circuit that sequentially delays the binarized output pixel by pixel, and a circuit that sequentially delays the binarized output pixel by pixel, and Noise removing means comprising a circuit that takes an AND of delayed outputs; a signal restoring means comprising a circuit that sequentially delays the AND output pixel by pixel; and a circuit that takes an OR of each delayed output and the AND output. I decided to connect them sequentially.

According to the present invention, it is possible to completely remove the pixel-by-pixel noise included in the binarized signal by the noise removal means, and the signal restoration means restores the pattern signal that has been lost due to the noise removal operation to its original proper state. Since the state is restored, alignment operations between patterns in pattern matching and pattern matching determination operations can be properly performed without being affected by noise, and object recognition accuracy can be greatly improved.

In addition, since noise removal is achieved using a simple hardware configuration that combines a shift ε register and a logic circuit, rather than using software processing, it can contribute to faster processing speeds, achieving the remarkable effects of achieving the purpose of the invention. play.

<Description of Embodiments> FIG. 1 shows the overall circuit configuration of a two-dimensional visual recognition device according to the present invention. In the figure, a television camera 1 images a stationary or moving object 2, for example from above, and sends an image output related to interlaced scanning to a synchronization separation circuit 3. The synchronization separation circuit 3 extracts a horizontal periodic signal HD and a vertical synchronization signal V from the image output.
D, odd field signal OD, clock signal CK, etc. are separated and the video signal VDi is outputted to the binarization circuit 4. 2
The digitizing circuit 4 sets a certain threshold level for the video signal VDi, binarizes the odd fields of the video signal VDi into black and white, and outputs a binarized signal A. A noise removal circuit 30, which will be described later, is connected to the binarization circuit 4, and this noise removal circuit 30 removes noise included in the binarization signal A in units of pixels. A reference memory 5 and a buffer memory 6 are connected to the noise removal circuit 30 via a mode changeover switch SW1, and when the mode changeover switch SW1 is set to the learning mode side 3 to image a standard model, the reference memory 5 is Standard pattern P (
il+) is stored in the buffer memory 6, and when the mode selector switch SW1 is set to the recognition mode side and the object to be recognized is imaged, the input switch Pi (shown in FIG. 2) is stored in the buffer memory 6.
(shown in FIG. 2(2)) are stored.

In the case of this embodiment, each pattern is stored in a pixel range of 256 bits in the vertical and horizontal directions, and in the example shown in FIG.
The input cover turn Pi is shifted toward the upper right with respect to the standard pattern P.

In the figure, horizontal counter 7.9 and vertical counter 8,1
0 specifies the pixel position in the memory when reading and writing the standard pattern P and the input pattern Pi, respectively.

Gate circuits 11, 12 and 13, 14 are controlled to open and close by odd field signal OD and clock signal CK.
A signal W defining an effective pixel range and a reset signal are supplied to each memory 5 and 6. Further, gate circuit 15 is controlled to open and close by odd field signal OD, and supplies clock signal CK to horizontal counter 7.9 and vertical counters 8 and 10, respectively.

A white pixel detection circuit 16 and a black pixel detection circuit 17 are connected to the noise removal circuit 30 via interlocking mode changeover switches sw1 and sw2, and a pixel counter 18 is further connected to these circuits via an OR circuit 25. has been done. The black pixel detection circuit 17 detects the black pixels (shaded area in FIG. 2) that constitute each pattern, and the white pixel detection circuit 16 detects the white pixels corresponding to the background area (the area other than the shaded area in FIG. 2). ) is detected. Furthermore, the pixel counter 18 is
When loading the pattern into each memory 5, 6, the output (number of white pixels) of the white pixel detection circuit 16 is counted at the same time timing, and the black pixel detection circuit 17 selects the first black pixel A,
When B is detected, the pixel number counting operation is stopped. The count data of the pixel counter 18 is I/1) (Input 1
0output) port 19 to the CPU (Central
alProcessing Unit) 20, and the CPU 20 calculates the positional deviation amount ΔX of the input cover turn Pi with respect to the standard pattern P from the counting results of the pixel counter 18 regarding the standard pattern P and the input cover turn Pi.
At the same time as calculating ΔY, these positional deviation amounts ΔX and ΔY are preset in the horizontal counter 9 and vertical counter 0 on the buffer memory 6 side, respectively.

Furthermore, an EXCLE-SIVE-OR circuit 26 (hereinafter referred to as EX-OR circuit 26) is connected to the readout output side of the reference memory 5 and buffer memory 6, and further EX,
The output side of the OR circuit 26 is connected to the pixel counter 8 via the OR circuit 25. Said EX, OR circuit 2
6 is used for pattern matching, and when the pixel data read from both memories 5 and 6 do not match, outputs a logic "1". Therefore, in this case, the pixel counter 18 calculates the number of mismatched pixels in both patterns. It will be counted. This counting data is sent to the CPU 20 +C via the I10 boat 19.
The CPU 20 displays this data content on the display unit 2.
7 and the reference value N set by the setting switch 28. Compare the size to determine whether the pattern matches or does not match. In the figure, PROM (Programmable
ReadOnly Me'mory) 21
stores a series of programs from positional deviation correction to object recognition, and also uses RAM (Random Acceg++
Memory) 22 has a work area for storing various data and for executing processing. Also gate circuit 2
3 is a circuit that generates an interrupt signal INT to the CPU 20, and an OR circuit 24 is a circuit that resets the pixel counter 18.

FIG. 2(1) shows the standard pattern P stored in the reference memory 5, and FIG. 2(2) shows the input pattern P stored in the buffer memory 6.
includes noises Nl and N2 corresponding to one to several pixels. In Fig. 2 (2), the chain line portion Pi' is the noise N.
1 shows a situation in which the position of the input cover turn Pi is erroneously recognized.

FIG. 3 shows a specific circuit configuration example of the noise removal circuit 30, and FIG. 4 shows a timing chart of which circuit.

The illustrated example circuit includes a noise removal unit 31 that removes noise equivalent to one pixel, and a signal restoration unit 3 that restores a pattern signal bone that is missing (one pixel missing) due to noise removal processing.
It consists of 2. The noise removal unit 31 removes the noise component n
The binarized signal A (shown in FIG. 4 (2)) containing the signal is delayed at the timing of the clock signal GK (shown in FIG. 4 (1)) to produce a delayed output B (shown in FIG. 4 (3)). The shift register 33 obtains a delayed output C(
2nd stage shift register 34 that obtains
and an AND circuit 35 that takes the logical product of both delayed outputs B and C, and the noise component n is removed from the logical product output D (shown in FIG. 4 (5)) of the AND circuit 35. In addition, the pattern signal bone P has a signal waveform with one pixel missing due to the noise removal operation.

The subsequent signal restoration unit 32 includes a shift register 36 that delays the AND output by one pixel to obtain a delay ratio (shown in FIG. 4 (6)), and a logical sum of the AND output and the delayed output I. The OR circuit 37 which takes ing.

FIG. 5 shows another embodiment of the noise removal circuit 30,
FIG. 6 shows a timing chart of this circuit. The circuit in the illustrated example includes a noise removal section 31 that removes noise equivalent to three pixels, and a signal restoration section 32 that restores a pattern signal bone that is missing (missing three pixels) due to the noise removal process. The noise removing unit 31 converts the binary signal A (shown in FIG. 6 (2)) containing the noise component n into the clock signal C.
K (shown in FIG. 6 (1)) to obtain a delayed output B (shown in FIG. 6 (3)); 2nd to 4th stage shift registers 39, 40, 41 that obtain outputs C, D, E (Figure 6 +4) T5+ +61
and each delay output B.

It also includes an AND circuit 42 that takes the logical product of C, D, and E, and the logical product output F of the at circuit 42 (see (7) in Fig. 6).
), the noise component n has been removed, and the pattern signal component P has a signal waveform missing three pixels due to the noise removal operation.

The subsequent signal restoration unit 32 sequentially delays the AND output F by one pixel to obtain delayed outputs G, l-I, I (sixth
(8) (9) (9) Includes three-stage shift registers 43, 44, and 45 for obtaining (shown in 101), and an OR circuit 46 that takes the logical sum of the AND output F and the delayed outputs G, H, and I. , and the OR output J of the OR circuit 46 (Fig. 6 0
1), the pattern signal portion P is restored to the original signal length.

However, when the standard model is imaged by the television camera 1 after setting the mode changeover switches sw1 and sw2 to the learning mode, binarization processing is performed for the first odd field of the video signal V D i, and after noise removal, the standard pattern is P is written and formed in the reference memory 5. Then, at the same time f timing, the output of the noise removal circuit 30 is sent to the pixel counter 18 via the white pixel detection circuit 16. An interrupt signal INT is generated to the CPU 2Q, and the count contents of the pixel counter 18 are read each time. In this counting process, when the black pixel detection circuit 17 detects the first black pixel A, the pixel counter 18 stops counting at that point. Therefore, the positions Xl and Yl of the first black pixel A are detected from the count contents of the pixel counter 18 and the counted number of scanning lines at this time, and these data are stored in the RAM 32.

When performing recognition processing for an object to be recognized, the mode changeover switch sw1. After setting sw2 to the recognition mode side 1), a similar imaging operation is performed.

In this case, the input cover turn Pi is stored in the buffer memory 6, and similarly to the above, the input cover turn Pi is loaded into 1 at the time timing of the odd field. Also, at the same time timing, the white pixel counting operation is executed, and the CPU 20 executes the counting operation for each horizontal blanking period.
An interrupt signal I N'r is generated for this. (When the black pixel detection circuit 17 detects the first black pixel B in the input cover turn Pi, the pixel counter 18 stops the counting operation at that point. Therefore, the counted contents of the pixel counter 18 at this time and the counted The position X2.Y2 of the first black pixel B is detected from the number of scanned lines.Then, the CPU2Q
calculates the positional deviation amount ΔX (-X2-Xl) in the same direction as the input cover turn Pi OX with respect to the standard pattern P and the positional deviation amount ΔY (=Y2-Y1) in the Y direction, and calculates these positional deviation amounts ΔX.

ΔY is preset in the horizontal counter 9 and vertical counter 10, respectively.

In the next even field, the horizontal and vertical counters 7.8 store the reference memory 5, and the preset horizontal and vertical counters 9, 10 store the buffer memory 6.
When the constituent pixel data of the standard pattern P and the input cover turn Pi are sequentially read out by addressing each of them, both patterns P and Pi are compared with each other with a positional shift of 7 (corrected overlapping state). When the pixel data do not match, the EX/OR circuit 26 outputs the logic “1j
The number of mismatched pixels is counted by the pixel counter 18. The CPU 20 is then interrupted every horizontal blanking period, and the contents of the pixel counter 18 are read out. When the same process is executed for all scanning lines, the content of the pixel counter 18 (total number of mismatched pixels) is displayed on the display unit 27, and the CPU 20 also displays the difference between the content of the pixel counter 18 and the reference value NO. compare. Then, when the count is the reference value No, which is small, it is determined that the input cover turn Pi matches the standard no-no turn ■', a match output is output, and the series of processing is completed.

[Brief explanation of the drawing]

FIG. 1 is a circuit block diagram of a two-dimensional visual recognition device according to the present invention, FIG. 4 is a timing chart of the circuit shown in FIG. 3, FIG. 5 is a circuit block diagram showing another embodiment of the noise removal circuit, and FIG. 6 is a timing chart of the circuit shown in FIG. 3. 3 is a timing chart of the circuit shown in the figure. 4... Binarization circuit, 30... Noise removal circuit, 31
... Noise removal section, 32 ... Signal restoration section, 33,
34°36.3B, 39,40,41,43,44°4
5...Shift register, 35.42...AND circuit, 37,46...OR circuit Patent applicant Tateishi Electric Co., Ltd.

Claims (1)

[Claims] Noise removal means comprising a circuit for sequentially delaying the binary output in pixel units, and a circuit for calculating the logical product of each delayed output, to the output side of a binarization circuit that converts the object image into black and white binarization;
A two-dimensional visual recognition device comprising a circuit for sequentially delaying the logical product output pixel by pixel, and a signal restoring means comprising a circuit for calculating the logical sum of each delayed output and the logical product output, which are sequentially connected.