JPS61880A - 2-dimensional visual recognizer - Google Patents

Abstract

PURPOSE:To obtain a 2-dimensional visual recognizer which can recognize quickly an object despite a shift of position of an input pattern, by detection quickly a position shift between a standard pattern and the input pattern and correcting said position shift on data. CONSTITUTION:A TV camera 1 picks up an object 2 and binary codes the video signal to connect these video signals to a standard memroy 5 storing a standard pattern and a buffer memory 6 storing an input pattern via a mode changeover switch SW1. When both patterns are fetched by both memories, the distance from the head black picture element train is measured by a counter for detection of each pattern position. In an input pattern fetching mode the position shift degree is calculated between both patterns while switching successively plural types of standard patterns. This shift is corrected on data and the input pattern is collated with each standard pattern. In such a way a process where the object 2 is positioned at a prescribed stop position is omitted and therefore the use of a special positioning mechanism is also omitted. Thus a 2-dimensional visual recognizer can be simplified as a whole.

Description

Detailed Description of the Invention <Technical Field of the Invention> The present invention obtains an input pattern by imaging a stationary or moving object to be recognized, and sequentially compares this input pattern with multiple types of standard patterns to identify the object to be recognized. In relation to a two-dimensional visual recognition device that recognizes a recognition object, the present invention particularly relates to a novel system that detects the amount of positional deviation of input patterns with respect to standard patterns, corrects the positional deviation between patterns, and then performs pattern matching. The present invention provides a two-dimensional visual recognition device.

<Background of the Invention> Generally, a two-dimensional visual recognition device recognizes an object by superimposing an input pattern and a standard pattern on an image, detecting the degree of superimposition and coincidence of both patterns. Therefore, when performing pattern matching, it is necessary to accurately align both patterns. Conventionally, an XY stage or the like is used to position the object to be recognized at a predetermined stop position, and then the object is imaged with a television camera to obtain the input pattern. The input pattern is matched against a standard pattern. However, this type of system requires a mechanism for positioning the object to be recognized, which complicates the overall structure of the apparatus and has many disadvantages, such as the time it takes for pattern matching to correspond to the time required for the positioning operation.

<Object of the Invention> The present invention accurately and quickly detects the amount of positional deviation of an input pattern with respect to a standard pattern, and corrects the position between patterns on the data. It is an object of the present invention to provide a two-dimensional visual recognition device that can quickly and easily recognize objects.

<Structure and Effects of the Invention> In order to achieve the above object, the present invention measures the distance to the first black pixel column with a counter and detects the position of each pattern when importing a standard pattern or an input pattern into a memory. When importing an input pattern, the input pattern is sequentially switched between multiple types of standard patterns, the amount of positional deviation of the input pattern with respect to each standard pattern is calculated, the position is corrected on the data, and the input pattern is compared with each standard pattern. I decided to do so.

According to the present invention, there is no need to position the object to be recognized at a predetermined stop position, no special positioning mechanism is required, the entire device can be simplified, and the time required for positioning operations can be saved, and object recognition is possible. Processing efficiency can be improved.

In addition, the position of each pattern is determined using a simple hardware configuration such as a counter, without using complex software processing such as image analysis.
Since the positional deviation between patterns is corrected, the input pattern can be compared with a plurality of types of standard patterns at high speed, which further contributes to an improvement in object recognition processing efficiency, and achieves the remarkable effect of achieving the purpose of the invention.

<Description of Embodiments> FIG. 1 shows an example of a circuit configuration of a two-dimensional visual recognition device according to the present invention. In the figure, a television camera 1 images a stationary or moving object 2, for example from above, and sends an image output (shown in FIG. 3(1)) related to interlaced scanning to a synchronization separation circuit 3. The synchronization separation circuit 3 extracts a horizontal synchronization signal HD, a vertical synchronization signal VD, an odd field signal OD (shown in FIG. 3 (2)), and a clock signal CK (shown in FIG. 3 (4)) from the image output.
) etc., and converts the video signal VDi into a binarization circuit 4.
Output to. As shown in FIG. 3 (3), the binarization circuit 4 sets a certain threshold level TH for the video signal VDi, converts odd fields of the video signal VDi into black and white binarization, forms a binary pattern, and outputs it. do. A reference memory group 5 and a buffer memory 6 are connected to the binarization circuit 4 via a mode changeover switch SWi.
Set the mode changeover switch SWl to the learning mode side a, and set the memory designation switch ss1. ss2. When capturing images of multiple types of standard models while selecting and operating the reference memos IJ Ml, M2, . For example, the standard pattern Pl+P2+... shown in FIG. For example, the input pattern Pi shown in FIG. 2 (2) is stored in 6. In the case of this example, each pattern has 256 pixels in the vertical and horizontal directions.
In the example shown in FIG. 2 (t1) 12+, the input pattern Pi is shifted in the upper right direction with respect to the corresponding second standard pattern p.

In the figure, horizontal counter 7.9 and vertical counter 8.1
0 specifies the pixel position in the memory when reading or writing the standard pattern P1 r PZ + . . . or the input pattern Pi. Further, gate circuits 11.12 and 13.14 are controlled to open and close by odd field signal OD and clock signal CK, and supply signal W defining the effective pixel range and reset signal k to each memory 5.6. Further, the gate circuit 15 is controlled to open and close by an odd field signal OD.
A clock signal GK is supplied to a horizontal counter 7.9 and a vertical counter 8.10, respectively.

The binarization circuit 4 includes an interlocking mode changeover switch s.
w1. A white pixel detection circuit 16 and a black pixel detection circuit 17 are connected via sw2, a pixel counter 18 is connected to the white pixel detection circuit 16 via an OR circuit 25, and another pixel counter 29 is connected to the black pixel detection circuit 17. are connected to each other. The black pixel detection circuit 17 detects the black pixels (shaded areas in FIG. 2) constituting each pattern, and the white pixel detection circuit 16
detects white pixels corresponding to the background portion (portions other than the shaded areas in FIG. 2). One pixel counter 18 counts the output (number of white pixels) of the white pixel detection circuit 16 at the same time timing when the pattern is loaded into each memory,
The black pixel detection circuit 17 detects the first black pixels A, A' (Fig. 4 f).
1++21), the pixel counting operation is stopped and the other pixel counter 29 then counts the output of the black pixel detection circuit 17 (the number of black pixels). The count data of these pixel counters 18 and 29 is sent to the CPU (Central Processes) via the I10 (Input Louput) port 19 every horizontal blanking period.
sing Unit) 20 D is taken in, c P
U 20 executes the calculation described later from the captured data and calculates the amount of positional deviation Δx1ΔY of the input pattern Pi with respect to the standard pattern.

Further, an exclusive OR circuit 26 (hereinafter referred to as EX, OR circuit 26) is connected to the readout output sides of the reference memory group 5 and the buffer memory 6, and EX,
The output side of the OR circuit 26 is connected to the pixel counter 18 via the OR circuit 25. Said EX, OR circuit 2
6 outputs a logic "1" when the pixel data read from both memories 5.6 do not match during pattern matching.Therefore, in this case, the pixel counter 18 counts the number of mismatched pixels in both patterns. It turns out. This counting data is taken into the CPU 20 via the I10 port 19, and the CPU 20 displays the contents of this data on the display section 27, and also sets the reference value N set with the setting switch 28.
Compare the size with O to determine whether the pattern matches or does not match.

If there is a match, the number of the standard pattern currently being matched is output, and if there is a match, the switching circuit 3
0! The next standard pattern is then selected. The illustrated switching circuit (9) includes an AND circuit 31 to which the mismatch signal π and the vertical synchronization signal VD are input, and the AND circuit 3.
A binary counter 32 that outputs an increment signal when two vertical synchronizing signals VD for the next odd field and the following even field are input; Each memory Ml of the reference memory group 5 performs a counting operation.

M2. . . . a pattern number counter 33 that outputs a signal for sequentially selecting . ... switch signal S
It includes OR circuits 34 and 35 to which ``1'', ``2+...'' are input.
21 stores a series of programs such as positional deviation correction, and also
M (Random Access Memory
) 22 has a work area for storing various data and for executing processing.

The gate circuit 23 also sends an interrupt signal I to the CPU 20.
This circuit generates NT, and the OR circuit 24 is a circuit that resets the pixel counters 18 and 29.

FIG. 4 (1) shows the second reference memory M of the reference memory group 5.
The standard pattern P stored in z is also shown in Fig. 4 (2).
indicate the input patterns Pi stored in the buffer memory 6, and in the figure, A' indicates the standard pattern P2.
and the first black pixel XASXA in the input pattern Pi
' is the position data of black pixels A, A', B, B' is the first black pixel A, the trailing black pixel of the black pixel row containing A', xB,
xB' is the black pixel B, position data c of B', c' is the reference point set at the center position of each black pixel column, Xl, X2
．． Yl and Yz indicate the position data of the reference points c and c', respectively, and the reference point C' of the input pattern Pi is shifted by JX in the horizontal direction and ΔY in the vertical direction with respect to the reference point C of the standard pattern Pz. are doing.

However, when the mode selector switches SWI and SW2 are set to the learning mode side a and the first standard model is imaged by the television camera 1 after pressing the switch SS1, for example, the first odd field of the video signal VDi is binarized. When the process is executed, the standard pattern Pl is written and formed in the first memory IJMl of the reference memory group 5. Then, at the same time timing, the output of the binarization circuit 4 is sent to the pixel counter 18 via the white pixel detection circuit 16, and the pixel counter 18 counts the number of white pixels, and at the same time, every horizontal blanking period. Interrupt signal IN to CPU20
T occurs, and the count contents of the pixel counter 18 are read each time.

FIG. 5 shows such an interrupt control operation, and in the figure,
xA is the count content of the pixel counter 18, 'XB-XA is the count content of the pixel counter 29, Yl is the count content of the row counter set in the RAM 22, and Fl is the count content of the same RAM 2.
2 shows the contents of the detection flag areas set in 2.

Assuming that the white pixel counting operation has been completed for the scanning line of Y1st Y1 (however, Y1 (256)), first the CP
ξU20 adds 1 to the content Yl of the row counter in step 41, and then checks in step 42 whether or not the detection flag F1 is the setting method.

This detection flag Fl is set when the pattern position is detected, and in this case, the determination is "NO".
Then, in the next step 43, it is determined whether the content XA of the pixel counter 18 has reached the number of pixel data of each scanning line (256 in this embodiment), that is, the first black pixel A is checked in the scanning of that line. It is checked whether or not it has been detected. If the pixel counter 18 has now counted the number of pixel data for one row (256 pieces) without being subjected to counting stop control by the black pixel detection circuit 17, step 43 becomes ``YES'', and step 44 then proceeds to step 44. , it is checked whether the contents of the line counter Yl have reached the final scanning line (256 lines in this embodiment).

In this case, since the determination in step 44 is 'No',
The process returns to the interrupt waiting state at the start, and a similar white pixel counting operation is executed for the next row.

In this counting process, when the black pixel detection circuit 17 detects the first black pixel, the pixel counter 18 stops counting at that point, and the other pixel counter 29 starts counting black pixels including the black pixel A from that point on. Start counting pixel columns. Therefore, in scanning this row, the content review of the pixel counter 8 does not reach r256J, and as a result, the determination in step 43 is 1NO in the interrupt processing for the next horizontal blanking period.
'The program then proceeds to step 45, where the contents of the row counter Yl are decremented by 1. Then, the CPU 20 performs step 4.
At 6.47, the contents of each pixel counter 18.29 XA,
XB-XA wo reading b Executing calculations of entry, exit, and luck to obtain position data xl of reference point C (step 48).

As is clear from the above equation, the reference point C is set at the center position of the first black pixel column, and the position data X1 and the content Y1 of the row counter are determined by the correspondence of the RAM 22 according to the determination result in step 49.50. The data is stored in the area (steps 51, 52).

In steps 49 and 50, any memory designating switch ss1. ss2. ... is turned on, and when the switch SS1 is turned on, step 49 returns #YE due to the generation of the switch signal Sl.
S', and for turning on switch SSz,
Step 50 is 'YES' due to the generation of switch signal Sz.
After storing the data Xl and Yl, the detection flag Fl is set in step 53, and 1 is added to the row counter content Yl in step 54, and step 41
will be returned to the state of

In the interrupt processing for each line below, rF in step 42
Since the determination of =IJ is #YES'', only the process of step 41 is repeatedly executed until it is determined in step 44 that the content of the row counter is Yir256J.

Then, when the determination in step 44 is 'YES',
In step 55, the content Yl of the row counter is cleared, and in step 56, the detection flag F1 is also reset.

When the processing for the first standard pattern P1 is completed as described above, the switch SS2 is then turned on and the same processing is executed for the second standard pattern P2. Furthermore, the same applies to the third and subsequent standard patterns, and after completing learning of all prepared patterns, the next step is to proceed to object recognition processing.

In this way, when performing the recognition process for the object to be recognized, after setting the mode changeover switches sw1 and sw2 to the recognition mode side, a similar imaging operation is performed. In this case, the input pattern Pi will be stored in the buffer memory 6, and writing of the input pattern Pi will be executed at the odd field time timing as described above. Further, at the same time timing, a white pixel counting operation is executed, and an interrupt signal INT is generated to the CPU 29 for each horizontal blanking period.

FIG. 6 shows such an interrupt control operation, and in the figure,
XA' is the white pixel count content of the pixel counter 18, and XB'
-xA' is the count content of the pixel counter 29, and Yz is the RA
The count contents of the row counter set in M22 are displayed in F2. F
8 indicates the contents of the detection flag and calculation flag set in the same RAM 22, and X8 indicates the contents of the mismatched pixel count of the pixel counter 18, respectively.

Assuming that the white pixel counting operation has been completed for the second scanning line of Y2 (F2<256), the CPU 20 first sets 1 to the content Yz of the row counter in step 61.
After addition, it is checked in step 62 whether the calculation flag F8 is the setting method or not.

This calculation flag F8 is set when the positional deviation correction process between patterns is completed, and in this case, the determination is "NO", and then in step 63 it is determined whether the detection flag F2 has been set or not. (in this case, 'No'), and further, in step 64, the content of the pixel counter 18 is
is the maximum number of pixel data (256 pieces) for each scanning line (in this case, 'YES')
Then, it is sequentially checked whether the contents of the line counter Y2 have reached the final scanning line (256 lines) (in this case, it is 1NO), and then the process returns to the state of waiting for an interrupt at the start point and starts the next line. A similar white pixel counting operation is performed for each row.

(When the black pixel detection circuit 17 detects the first black pixel A' in the input pattern Pi, the pixel counter 8 stops counting at that point, and the other pixel counter 29
starts counting the black pixel columns including the black pixel A' from that point. Therefore, in scanning this row, the pixel counter 8
The content xA' does not reach r256J, so the determination at step 64 becomes 'No' and the process proceeds to step 66.
The contents of the row counter Y2 are decremented by 1. Then CPU2
0 reads out the contents XKx'
).

Furthermore, in step 70.71, the CPU 20 calculates the respective positional deviation amounts ΔX and ΔY in the X direction and the Y direction of the input pattern Pi with respect to the first standard pattern P1 using the following equations.

Δx = X2-Xl ΔY = F2-Y.

Thereafter, the detection flag F2 is set in step 72, and in the following step 73, 1 is added to the content Yz of the row counter to return to the state of step 61.

(When the content Y1 of the row counter reaches "256", step 65 becomes ``YES'', and in the next step 74, the positional deviation amount ΔX is stored in the horizontal counter 9, and the positional deviation amount ΔY is stored in the vertical counter 10. After presetting each,
In steps 75-77, the content Yz of the row counter is cleared, the detection flag F2 is reset, and the calculation flag Fa is cleared.
Set.

Then, in the next even field, the reference memory 5 is addressed by the horizontal and vertical counters 7.8, and the buffer memory 6 is addressed by the preset horizontal and vertical counters 9.10, respectively, and the standard pattern Pl and the input pattern are addressed. When sequentially reading constituent pixel data of Pi, both patterns P1. The data of Pi will be compared in an overlapping state in which positional deviations have been corrected. As a result, when both pixel data do not match, the EX/OR circuit 26 outputs a signal of logic "1", and the pixel counter 18 counts the number of mismatched pixels.

Then, an interrupt is generated to the CPU 20 for each horizontal blanking period, and after 1 is added to the row counter content Y1 in step 61, a ``YES'' determination is made in step 62, and the content X8 of the pixel counter 18 is added to the pixel counter 18 content X8 in step 78. are read out and added one after another. When the same process is executed for all rows, rYz=25 in step 79.
6J becomes 'YES', the content Xa (total number of mismatched pixels) of the pixel counter 18 is displayed on the display section 27 in the next step 80, and the CP
U20 compares the content x8 of the pixel counter 18 with the reference value NO. And the count content x8 is the standard value 86
If this is the case, it is determined that the input pattern Pi does not match the first standard pattern Pl, and the process proceeds to step 82, where the pattern number counter 33.
Whether the content N is the maximum or not, that is, the switching circuit 30
It is checked whether the final standard pattern has been selected. In this case, the determination at step 82 is 'No.
', the content N of the pattern number counter 33 is incremented by 1 in step 83, the next standard pattern P2 is selected, and furthermore, after the calculation flag F8 is cleared in step 84, the process returns to the interrupt start point and the same processing is performed. is executed repeatedly.

As a result, the positional deviation amounts ΔX and ΔY of the input pattern with respect to the second standard pattern P2 are detected (step 70.7
1), presetting of the positional deviation amounts ΔX and ΔY to the horizontal and vertical counters 9.10 (step 74), and reading out the number of mismatched pixels (step 78), etc. are sequentially performed.

As a result, the determination of rXa<'NOJ in step 81 is '
When the answer is YES', in step 85, based on the count N of the pattern number counter 33, the CPU 20
outputs the pattern number and outputs a coincidence signal in step 86, then returns the content N of the counter 33 to the initial state "1" in step 87, and clears the calculation flag F8 in step 84.

Note that when the input pattern Pi does not match any standard pattern, the determination at step 82 becomes 'YES#', and at step 88 the CPU 20 selects an unrecognizable output.

[Brief explanation of drawings]

FIG. 1 is a circuit block diagram of a two-dimensional visual recognition device according to the present invention, FIG. A timing chart showing signal waveforms of the circuit configuration example shown in FIG. FIG. 6 is a flowchart showing the interrupt processing operation in the recognition mode.

Claims (2)

[Claims] (1) After obtaining an input pattern by converting the image of the object to be recognized into black and white, the device recognizes the object by comparing the input pattern with a standard pattern. 1 memory, a second memory for capturing the input pattern, a counter for measuring the distance to the first black pixel column for each pattern, and a positional shift amount of the input pattern with respect to the standard pattern based on the measurement result of the counter. A two-dimensional visual recognition device comprising: an arithmetic processing unit that detects and corrects the patterns, and then compares both patterns; and a switching device that sequentially switches between multiple types of standard patterns to be compared. (2) The two-dimensional visual recognition device according to claim 1, wherein the counting process of the counter is performed in parallel at the same time as the pattern is taken into the memory.