JPS60263529A - Expanding circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a decompression circuit, more specifically, a nonlinear compression PCM.
An expander that converts the signal into a linear PCM signal suitable for digital signal processing, especially μ-law or A-law PC for telephone voice communications.
The present invention relates to a suitable decompression circuit that implements a codec that inputs and outputs M signals using an LSI.

[Background of the invention]

Figure 1 shows the configuration of a PCM codec that uses digital signal processing technology to mutually convert an audio signal into a linear PCM signal, a μ-law or A-law compressed PCM signal.Input audio 1-1 is an A//D After converting into a linear PCM signal with a converter 3, a band-limiting filter 4 consisting of a digital circuit is applied.
filters only the voice band, and converts it into a μ-law or A-law 8-bit compressed PCM signal 2-1 in a compressor 5 based on CCITT recommendations, and outputs it to the PCM highway. On the other hand, input compression P
The CM signal 2-2 is converted into a linear P of 13 pitches or more by the expander 8.
After converting to a CM signal, a digital reduction filter 7 (
The D
/A converter 6 converts it into audio analog signals 1-2. Incidentally, recently, there has been an increasing demand for codec LSIs to have multiple functions, and it has become necessary to incorporate one of them, the king call function. For the sake of simplicity, we will explain the receiving side regarding this champion call function. As shown in the example shown in Fig. 2, the champion's signal (B and C) is transmitted in one frame (125 μs) with a period corresponding to the sampling frequency of 8 kHz. ) in the designated time slots CH(1) and CH(n), respectively.
The two signals are taken into the codec as compressed PCM signals, each converted to a linear P'CM signal, and then both are added together.
The combined digital signal is passed through the LPF and D/A converter shown in FIG. 1, and a combined analog signal of B and C is output. Here, it is preferable that the designation of time slots for B and C is arbitrary based on the system configuration, so for example, for CH
Adjacent cases such as CH(1) and CH(2) also occur. In this case, the bit rate (transmission frequency:
fp) and the decompressor's conversion time Td, in order to continuously convert the decompressor into a linear signal at the same clock frequency as the decompressor's conversion time Td, the decompressor must be duplicated and built in, or the decompressor must be used in time division multiplexing. In order to make this possible, a register is required to temporarily store the PCM signal of either compressed signal B or C. Furthermore, considering the system configuration, the conversion time T
Since d relates to the absolute delay time of the codec, it is preferable that it be as short as possible.

By the way, as mentioned above, the companding code rules used in PCM communication are based on the CCITT (International Telegraph and Telephone Consultative Committee).
There are μ-law and A-law of Recommendation, G, 711, and each compression PCM
The relationship between the signals and the corresponding linear PCM signals is summarized as shown in FIG. 3 for the μ-law and FIG. 4 for the A-law. In FIG. 3(a), Pl and P2 to P8 represent the polarity and amplitude of the compressed PCM signal;
P4 indicates a segment, and P5 to P8 indicate step information.

In addition, in the same figure (b), B1 is the polarity, B2 (MSB)
~B14 (LSB) is the amplitude value of the linear signal to be converted plus 33. FIG. 4 is similar to FIG. 3, but FIG. 4(b) corresponds to the value itself to be converted.

As a conventional parallel processing decompressor for the μ law, there is the C'A Unified Formula, an example of which is shown in FIG.
ation of Segment Co+spandi
ng Laws and 5 synthesis of C
odees and Digital Compand
ors, “the Bell Sestam Tech
nical Journal, September
1970 P.

1555-1588). The step information V= (P5.P6.P7.P8) of the compressed PCM signal is converted into a pattern corresponding to (1 hair 1 for 1 person) in FIG. (hereinafter referred to as SR) 2-1. On the other hand, segment information t, = (p2.p3
．． T'4)1. t binary down iy un! i (hereinafter referred to as BC)
3-1, and at the same time, SR is shifted to the left at clock 4-1 until the BC output becomes (0, 0, O), and l# Opg is input from the right.

As a result, the SR output when all the BC outputs are 410H matches the pattern shown in FIG. 3(b). Therefore, by subtracting 113377 with the parallel adder 1-2, the desired linear FICM signal can be obtained. however,
Although not shown in the conventional example, the above signal is expressed in folded binary notation. In order to input this to the digital signal processing circuit connected to the subsequent stage as shown in FIG.
It is necessary to convert it into a two's complement representation signal suitable for the processing. That is, in order to put the conventional example into practical use, in addition to the circuit described above, an adder for converting the complement representation described above is required separately.

Furthermore, in order to obtain the pattern shown in Figure 3(b), it is necessary to reset the contents of SR before storing the output of adder 1-1 in SR, so SR is realized by a shift register with a reset function. Must. By the way, in this conventional example, conversion time corresponding to the maximum clock time is required depending on the segment information. Therefore, when the clock frequency f is low, not only does the absolute delay time of the entire codec increase correspondingly, but also the decompression conversion time Td (=7/f
) cannot satisfy the bit rate conditions of the input 8-bit compressed PCM signal, as mentioned above, it is necessary to duplicate the decompressor or to use a register for temporary storage of the input compressed PCM signal, which increases the amount of hardware. .

[Purpose of the invention]

Therefore, the purpose of the present invention is to solve the above-mentioned drawbacks and to provide an input compression PC.
An object of the present invention is to provide a high-speed decompressor circuit that can be used continuously in time division multiplexing even if the bit rate of an M signal is high.

[Summary of the invention]

In order to achieve the above object, the present invention uses an input compressed PCM
- The signal conversion shown in FIGS. 3 and 4 is realized from the amplitude bits P2 to P8 of the signal using a combinational logic circuit.

Conversion to two's complement representation is performed in parallel once, and then a parallel adder is used to simultaneously perform 33 subtraction. As a result, the process from inputting the compressed PGM signal to converting it to a two's complement display signal can be accomplished within one clock.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described in detail using FIGS. 6 and 7.

First, a case will be described in which a μ-law pressure line PCM signal is expanded into a linear PCM signal. At this time, each changeover switch function 6-1 to 6-4 in FIG. 6 and 6-5 in FIG. 7 are connected to the μ terminal side. In FIG.
In the combinational logic circuit 1 whose specific example is shown in -, the third
The pattern is converted to the pattern (B2 to B14) shown in Figure (b). However, at this time, if the amplitude absolute value of the desired linear PCM signal is Y, B2-B14 is the value of (Y+33). When the polarity of the input compressed PCM signal is positive (i.e., Pt="t" (high logic level)), the linear PCM
The output of inverter 2-1 that gives signal polarity B1 is #0
11 (low logic level), this B1 and B2
-B14 is directly supplied to one input terminal B of the 14-bit parallel adder 4 through the exclusive OR circuit 3. On the other hand, each of the other input terminals A of the parallel adder 4 receives "11111111011111" from the most significant (polarity) bit adder 4-1 to the least significant bit adder 4-14.
However, the carry input terminal CI of 4-14 has '0'.
″″ is supplied. The signals supplied to terminals A and CI mean the value -33 expressed in two's complement, so in the end,
The parallel adder 4 will output the calculation result of (Y+33)-33, and the desired two's complement representation will be displayed on the linear PC.
M signal Y can be obtained.

Then the polarity of the input compressed PCM signal is negative (i.e. P1=
In the case of "Q'"), the inverter output B1 becomes 1"', so the output of the exclusive OR 3 becomes the one's complement of the value (Y+33) represented by B2-B14, that is, -(Y+34). On the other hand, the parallel adder 4 supplied from the logic circuit section 5
The signals at each input terminal A of are in the same order as in the positive case described above.
o o o o o o o o o o o o o o o
o i'', which means +33, but at this time, the carry manual CI of the adder 4-14 of the least significant bit
becomes '1'', so in the end, the parallel adder 4 becomes -(Y+3
4) The calculation result of +33+1 is output, and the desired linear PCM signal -Y expressed in two's complement can be obtained.

Next, the case of rule A will be explained. There are three differences in the extension conversion in the case of the A-law compared to the case in the μ-law. These differences will naturally become apparent by comparing Figures 3 and 4. The first point is that the odd bits of the compressed PCM signal representing the same analog value are inverted.

Therefore, in the decompression circuit of the present invention, in order to make the relatively complicated rotating part as common as possible, the odd bits (P3, P5, P7) of the A sub-compressed PCM signal are inverted and supplied to the logic circuit 1, which will be described later. There is. Changeover switch function 6- in Figure 6
2.6-3.6-4 is provided for this purpose. Next, the second difference is that the step bit (
Contents A, B, C, and D of P5 to P8) are shown in Figures 3 and 4.
As is clear from comparing the tables (b) in the figure, the A-law is shifted by one bit in the upper direction with respect to the μ-law. The changeover switch function due to this second difference is performed by 5-6 in the logic circuit section 1 (see FIG. 7, which will be described later). The third difference is that if the conversion results from (a) to (b) in FIG. This means that there is no need to make 33 corrections as in the case of the μ law. The switching function of this third difference is the switch 6-1. That is, when the polarity of the input compressed PCM signal is positive (P1="1'"), B1 is #Opg, so the output cover turn (B2-B14) of the logic circuit section 1 shown in FIG. 4(b) is are directly supplied to each input terminal B of the parallel adder 4 through the exclusive OR 3. On the other hand, at this time, each of the other input terminals A of the parallel adder 4 and the carry input terminal of the adder 4-14 for the least significant bit. Next, when the polarity of the input compression signal is negative (PL=10''), B1="1", so
The output of exclusive OR 3 is expressed as a 1's complement number, but at this time, the carry CI of the addition of the least significant bit @4-14 is I
I11g, so that the parallel adder 4 can output the two's complement representation result of the output of the logic circuit section 1.

Next, an embodiment of the logic circuit section 1 shown in FIG. 6 which performs the conversion shown in FIGS. 3 and 4 will be described with reference to FIG.

In the case of μ law, the signal patterns of the input terminals D2 to D8 of the logic circuit section of FIG. 6, that is, the logic circuit of FIG. 7, match input compressed PCM signal patterns P2 to P8 as they are, so for example, 'P2. P3゜P4. P5. P6. P7. P
8” = “1110000” (7), X = “1”, the output of the inverter (1-1 to 1-7. and 1-9) is “0”
'', other inverters (l-8, and 1-1O to 1-
The output of 13) is u I II. Therefore, (1
), (2), (4).

Outputs B9 to B corresponding to (7), (11) and (16)
14 becomes #1 tt, and the other outputs become 0'', so the conversion shown in Figure 3 can be realized.On the other hand, A
In the case of the rule, “P2.P3.P4.P5゜P6.P7
．． P8''="1011010", the signal pattern of the corresponding input terminals D2 to D8 will be the same as in the case of μ law, however, if X = #l 01y, inverter (
1-1 to 1-6. and 1-8) output is ffl O#l
, other inverters (1-7 and 1-971-13)
The output of is II 1 ##, therefore, only outputs B9 to B13 corresponding to switch rows (3), (5), (8), (12), and (17) become "1"", and other outputs becomes 0#, so the conversion shown in FIG. 4 can be realized accurately.

By the way, the embodiment shown in FIG.
, NOR and other logic gates, programmable logic arrays, read-only memories, etc.
Therefore, the circuit configuration is not particularly limited to this embodiment. Also, μ law and AJ [! The I switching function is also controlled by external signals.

Furthermore, it goes without saying that if it is implemented as an LSI, it can be easily realized by changing the wiring mask or the like.

Therefore, as described in detail above, according to the present invention, decompression conversion from μ-law and A-law compressed PCM signals to linear PCM signals expressed in two's complement suitable for digital signal processing can be performed without using a clock. Therefore, it can be realized at a high speed other than one clock cycle, and there is no particular increase in hardware requirements, so it can be realized economically in an LSI.

[Brief explanation of drawings]

Figure 1 is a block diagram of a codec using digital signal processing technology, Figure 2 is a diagram of the relationship between the three items in the codec, Figure 4 is a diagram of the relationship between compressed PCM signals and linear PCM signals in A-law, and Figure 5 is a diagram of the relationship between compressed PCM signals and linear PCM signals in A-law. A conventional example is shown in Fig. 1.1-1...Input audio signal, 1-2...Output audio signal, 3...A/D converter, 4...Band filter, 5...
... PCM compressor, 2-1... Output compressed PCM signal,
2-2... Input PCM compressed signal, 6... D/A converter, 7... Low pass filter, 8... PCM expander, Fig. 5 1-1 to 1-2...・Parallel adder, 2-1...Shift register, 3-1...Binary down counter, 4-1.
...Clock, 5-1...NOR circuit, 6-1...
AND2nd cs tyr) --! 1-----'-X 3 Figure ((L) (b) Figure 5-1

Claims (1)

[Claims] The 1st bit is the polarity, the 2nd to 4th bits are the segment number, and the 5th to 8th bits are the step number.The A-subvalve linearly compressed PCM signal is converted into a 14-bit linear PCM signal expressed in two's complement. In the converting decompressor, in the case of μ law, 33 is added to twice the value represented by the above step number to give 2'm (where m is 1 to 1 which matches the segment number).
In the A-law, the compressed PCM signal is the first
For signals with a minimum of 16 steps or less among 32 steps in a segment, 1 times the value represented by that step number.
A combinational logic circuit is used to convert the value obtained by adding and doubling the value, which is also the A-law and the same value as the μ-law for signals above the above, into a linear PCM signal with an amplitude of 13 bits, each of which is expressed as an absolute value. a first logic conversion circuit constructed using the above-mentioned first logic conversion circuit; a second logic conversion circuit that converts the output signal of the first conversion circuit into a one's complement display signal; Bit-parallel adder, -33 expressed in two's complement for a positive μ-law compressed signal, +34 for a negative μ-law compressed signal, and 0 for a positive A sub-compressed signal. and a third logic conversion circuit which similarly outputs +1 for the negative A sub-compressed signal and uses the other input of the parallel adder and the least significant bit as a carry six. A decompression circuit.