JPS602700B2 - Program sequence detection device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a program sequence detection device that detects whether a predetermined program sequence has been executed in an information processing device.

Conventionally, when trying to detect this type of program sequence, the conditions for starting or ending a test are set by comparing input information from the device under test with information specified by a switch on the measuring instrument. It was being done.

Normally, this switch has three positions, and the comparison condition is specified as either to compare with the expected value consisting of "1" and "0", or as "n'tCa ratio" (no comparison), and the input information is When the information matches the information specified in the switch, a test start or test end signal is generated. The disadvantage of this example is that only one condition for the test start or test end signal can be set, and cannot be set as sequential events that change over time. In particular, when you want to measure information processing events that are processed by program control or microprogram control, you often want to specify the test start or test end conditions as a sequence of program addresses. Setting is not possible. An object of the present invention is to store in advance a program sequence to be detected in a storage circuit as a set of expected values including comparison information, mask information, and control information.
By successively comparing the input information sent from the information processing device with the expected value in the storage circuit in synchronization with the control signal sent from the information processing device,
The present invention provides a device that can detect any program sequence.

The present invention includes an address storage means for temporarily storing the address of an instruction executed by an information processing device, an address to be detected that is arranged in a sequence to be detected, and includes at least a test start address and a test end address of a program sequence; storage means for storing control information indicating whether or not the address is a test end address; and a match signal when the address stored in the address storage means and the address to be detected stored in the storage means match. and a comparison means for outputting at least the next address to be detected in the storage means when a match signal is output from the comparison means when the control information from the storage means does not instruct the end of the inspection. supplying the data to the comparison means, and when the control data instructs the end of the inspection and a match signal is output from the comparison means, outputting a signal indicating that the corresponding program sequence has been detected; The program sequence detecting device is characterized in that it includes means for supplying the address of the test start address to the comparing means when the matching signal is not supplied from the comparing means.

Next, an embodiment of the present invention will be described with reference to the drawings.

Referring to FIG. 1, one embodiment of the present invention can be roughly divided into an input circuit 4, a comparison circuit 5, a control circuit 6, and a storage circuit 7.
It consists of The input circuit 4 receives an input circuit 2 including a program address or a microprogram address and a control signal 3 indicating the timing of receiving the information from the information processing device 1, performs level conversion, etc., and then outputs the input information 16 and the control signal. 17 to the comparison circuit 5 and control circuit 6. The storage circuit 7 stores the program sequence to be detected as a set of expected values including control information, comparison information, and mask information, and when it receives the pickup signal 11 and address signal 12 from the control circuit 6, it starts the reading operation. Thereafter, comparison information 8 and mask information 9 are sent to the comparison circuit 5, and control information 10 is sent to the control circuit 6. The comparison circuit 5 compares the input information 16 sent from the input circuit 4 with the comparison information 8 sent from the storage circuit 7, and sends the comparison result to the comparison instruction signal 13 sent from the control circuit 6. In response, a comparison result signal 14 is sent to the control circuit 6. Note that the input information 16 and the comparison information 8 are composed of the same number of bits, and the comparison method is to compare the input information 16 and the comparison information 8.
The control circuit 6 generates a read signal 11, an address signal 12, and a comparison instruction signal 13 in synchronization with the control signal 3 sent from the information processing device 1, and when all pre-designated program sequences are detected. An event detection signal 15 is sent to the measuring instrument. Next, the operation will be explained.

First, a predetermined expected value is stored in a storage device for initial preparation. When the above preparations are completed and the operation starts, input information 2 and control signal 3 are sent from the information processing device 1. When the control circuit 6 receives the control signal 17 corresponding to the control signal 3, the control circuit 6 transmits an address signal 12 and a shortcut signal 1 to the storage circuit 7.
Sends 1. In this case, since the operation is started, the initial value (starting address) of the address signal 12 is sent out. When the memory circuit 7 receives the reading signal 11, it reads the expected value from the address indicated by the address signal 12, and sends the comparison circuit 5 and the control information 10 to the control circuit 6. Mother. Next, the control circuit 6 sends a comparison instruction signal 13 to the comparison circuit 5. Upon receiving the signal, the comparison circuit 5 converts the input information 16 and comparison information 8 into mask information 9.
The results are compared using the method described above under the control of , and the results are sent to the control circuit 6 as the Himisaki shark result signal 14. The control circuit 6 receives the comparison result signal 14 according to the instructions of the control information 10 as described above. The above are parts that operate in common based on any information, and the parts described below operate differently depending on the control information.
First, an overview of the control information will be explained. Figure 2 shows
2 shows the format of the expected value of the program sequence to be detected, which is stored in the memory circuit. One word consists of control information that instructs the control circuit 5 to perform various controls, comparison information that indicates information to be compared with the input information 2, and mask information that indicates bits to be compared.

Next, control information will be explained.

The control information has two main functions. The first function is that of the first bit (leftmost bit) of the control information, and this bit indicates the end of the expected value information. That is, if the first bit is "1", and if the comparison result with this expected value matches (result 14 = 1), the event detection signal 15 is sent to the measuring instrument and the operation is terminated. show something However, if there is a mismatch (comparison result signal 14=0), the address signal 12 is returned to its initial value (starting address). Second
The function of is to indicate the number of dummy steps in the area after the second bit. Here, the dummy step refers to a step in which the comparison result signal 14 is ignored and the address signal is not updated. With this function, there is no need to compare. The gram sequence can be skipped, and the expected value information stored in the storage circuit 7 can be reduced. An example of a dummy step is shown below.

Example of a dummy step The state of a certain step (supposed to be So) is as follows.

This is stored in the memory circuit 7 in an initial state. Address signal 12=Ao Ratio comparison date information 8=Eo Number of dummy steps=n Input information 2=No Note that the number of dummy steps has the following meaning depending on its value.

If 0: A dummy step is not inserted and the comparison result is immediately received.

1 to n (n and all 1): Receive the comparison result after executing n dummy steps.

In the case of all: Do not proceed to the next period value until input information equal to the comparison information indicated in this expected value appears.

These states change as follows each time the step signal advances (that is, each time control signal 3 is received), and eventually n
You can see that a dummy step has been added.

Next, the expected value of the program sequence to be detected before the start of operation is stored in the storage circuit 7 in the format shown in FIG.

To make the explanation easier to understand, Table 1 shows an example of the instruction sequence to be executed. In Table 1, the case where the dummy step is 0, that is, the case where addresses corresponding to the instructions to be detected are stored one by one will be explained.

Table 2 In this case, address a of execution order 1 listed in Table 1
and the address a stored in the memory circuit 7 listed in Table 2 are compared, and since they do not match, the address b of the next execution order 2 is compared with the address b listed in Table 2. .

Through this repetition, up to address d are compared, and then address e of execution order 5 is compared with address f stored in memory circuit 7 listed in Table 2. Since the end instruction is indicated and the comparison result is a mismatch, address a, which is the test start address, is compared with address a, which is in the execution order 6.
Even if another address other than address a is executed at this stage, comparison will continue until address a, which is the test start address, is executed. In the same repeat, execution order 1
If the address f of No. 5 matches the address f which is the expected value, an end signal is output because an end instruction has been given. This end signal indicates that the command group of the program sequence shown in Table 2 has been executed. Next, if the dummy steps are not all, the number of dummy steps is 1.
An example is shown in which the number of times is ˜n (n all) times. For example, assume that the contents shown in Table 3 are stored in the storage circuit 7. Table 3 The operation in this case is the same as the relationship between Tables 1 and 2 up to the point where address a is compared.

Next, there are three consecutive steps of addresses with dummy information of 1.
In other words, no comparison is made using the comparison means during this period. However, at the fourth step, execution address a of execution order 5 is compared with address f, which is the expected value, and a mismatch signal is output. In this case, since an end instruction has been given, address a, which is the test start address, will be compared with the next execution address a. The subsequent operations are similar to the relationship between Tables 1 and 2. Next, if the dummy information is all, the contents stored in the memory circuit 2 may be the contents shown in Table 4. Table 4 In other words, the operation in this case is that address information a in execution order 1 is first compared with address information a which is the expected value, and since the comparison results match, the next expected value to be compared is becomes d.

This means that even though execution orders 2 and 3 are compared with the expected value d, they do not match. As a result, address information d of execution order 4 is next compared with address d, which is the expected value, and since the comparison results match, the next expected value to be compared is f. However, since the address information of execution order 5 is e, the comparison result does not match. Moreover, since the end instruction has been given, the address information of the next execution result will be compared with address a, which is the test start address. This process is repeated until the address f in execution order 15 matches the address f which is the expected value, and in this state a termination signal is output. Note that the dummy information is not necessarily necessary if the relationship between Table 1 and Table 2 and the relationship between Table 1 and Table 3 are clear in advance. Alternatively, mask information may be stored together with the comparison information, and only comparison information that is not (or is) masked by the mask information may be compared.
As explained above, by adopting the configuration shown in FIG. 1, the present invention provides a measurement start signal or a measurement end signal based on a complex program sequence event to a measuring instrument such as a logic analyzer. This has the effect of making it possible to send signals.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, and FIG. 2 shows the format of expected values in the memory circuit. 1... Information processing device, 2, 16... Input information, 3, 17... Control signal, 4... Input circuit,
5... Comparison circuit, 6... Control circuit, 7...
...Light circuit, 8...Comparison information, 9...
・Mask information, 10... Control information, 11...
・Read signal, 12...Address signal, 13...
...Comparison instruction signal, 14...Comparison result signal, 1
5...Event detection signal. Spear' figure O2 figure

Claims (1)

[Claims] 1 address storage means for temporarily storing the address of an instruction executed by an information processing device; an address to be detected arranged in a sequence to be detected and including at least a test start address and a test end address of a program sequence; storage means for storing control information indicating whether the address is an end address; and outputting a match signal when the address stored in the address storage means and the address to be detected stored in the storage means match. a comparison means; when the control information from the storage means does not instruct the end of the test and a match signal is output from the comparison means, at least the next address to be detected in the storage means is sent to the comparison means; and when the control information indicates the end of the test, when the comparison means outputs a matching signal, outputs a signal indicating that the corresponding program sequence has been detected, and the control information indicates the end of the test. A program sequence detecting device comprising: control means for supplying the address of the test start address to the comparing means when the matching signal is not supplied from the comparing means in the case where the matching signal is indicated or not indicated.