JPS6027129A - Method for annealing metallic film wiring - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for annealing metal film wiring in semiconductor devices and the like.

[Prior art]

FIGS. 1A to 1D are cross-sectional views showing the main stages of a conventional method for forming metal film wiring, taking a MO8 structure semiconductor device as an example. First, as shown in FIG. 1(a), a relatively thick silicon field oxide film (2) for isolation and insulation is selectively formed on a substrate (1) made of silicon (Si), for example. Subsequently, as shown in FIG. 1(h), a relatively thin silicon oxide film (3) for a gate is formed on the substrate (1), and impurity doping for controlling the threshold voltage of the transistor is doped therebelow. Layer (4) is formed by a method such as ion implantation. next,
As shown in FIG. 1(c), a polycrystalline silicon film (5) and a low resistance film (6) of a high melting point metal or high melting point metal silicide for forming a low resistance gate electrode are formed on the polycrystalline silicon film (5) by sputtering, CVD, electron It is formed by a method such as beam evaporation, and then photoresist yA (7) is applied as an etching mask.
(d) selectively place. Next, as shown in Figure 1←, a photoresist film (
Using 7) as a mask, the low resistance film (6) and the polycrystalline silicon film (5) are selectively etched in order, and the silicon oxide film for gate (3) is also etched to remove the impurity doped layer (4). Silicon gate oxide film (3a) on top,
polycrystalline silicon gate) (5a) and gate wiring (6a)
) are formed so as to overlap one another. Thereafter, the gate wiring (6a) made of a high melting point metal or its silicide is annealed in a diffusion furnace as shown in FIG. 2 in order to further reduce the resistance. (8) is an oxide film produced at that time. Thereafter, as is well known, impurities such as arsenic (A8) are introduced into the main surface of the substrate (1) by ion implantation or the like in a self-aligned manner, and heat treatment such as annealing/drive is performed to form the source region (9) and A drain region CI0 is formed.

By the way, FIG. 2 was used for annealing to lower the resistance of the gate wiring (6a).

Figure 2 is a schematic cross-sectional view showing the structure of a conventional diffusion furnace used for this annealing, where αυ is the furnace body, (6) is the gas inlet, a is the heater, and Q is the semiconductor wafer to be processed. It is. When annealing is performed in such a diffusion furnace, if it contains metals that are easily oxidized (such as titanium), the furnace body 0])
When it is taken in and taken out of the oven, it comes into contact with the air at a high temperature, so a metal or silicon oxide or nitride film (8) forms on the surface as shown in Figure 1(d), making it impossible to achieve a satisfactory low resistance. . This phenomenon is remarkable when titanium or titanium silicide is used, and a titanium oxide film is formed.

Additionally, there may be no problem if the furnace temperature is lowered when loading and unloading from the furnace, but diffusion furnaces are constructed to maintain good temperature, so there are problems such as the need for a long time to raise and lower the temperature. was there.

[Summary of the invention]

The invention was made in view of the above points, and by using an annealing furnace that can raise and lower the temperature in a short time and can replace the gas in the chamber or create a vacuum, it is possible to remove the heat from the furnace. The present invention provides a method for stably forming low-resistance metal film wiring without being affected by air during loading and unloading and annealing.

[Embodiments of the invention]

FIG. 3 is a schematic cross-sectional view showing a configuration example of an annealing apparatus used in the present invention, αQ is a chamber with a small heat capacity, 01
G is the lid of the sample loading/unloading port, (I'?) is the gas inlet, (G) is the gas outlet, and Q is the heating lamp (a heater may be used). ) (however, the oxide film (8) is not formed because no annealing has been performed) is placed in the chamber α, sealed with a lid α, and the gas inlet is closed. Introduce the required inert gas from Q71 and open the gas outlet (
After the inside of the chamber is made into an inert gas atmosphere by discharging the wafer from the semiconductor wafer /.alpha., the semiconductor wafer/.alpha. When the annealing is completed and the power to the heating lamp α is cut off, since the heat capacity at the time of channel -α is small, the temperature rapidly decreases, and the temperature of way/SQ→ also decreases rapidly. Therefore, even if the wet α→ is taken out into the air and comes into contact with oxygen and nitrogen, no oxide film or nitride film (8) is formed on the surface of the metal film.

Therefore, a sufficiently low resistance film can be obtained by annealing without hindering the reduction in film resistance due to annealing as in conventional methods. For example, argon (Ar) gas is suitable as the inert gas, and it goes without saying that instead of using an inert gas, annealing may be performed with the inside of the chamber in a vacuum state.

Using this method, we prototyped a MOS transistor using titanium silicide for the gate wiring, but no oxide film was formed on the surface, and the sheet resistance was 2 times the thickness of the titanium silicide film.
000 people, it was about 0.8Ω/-. In addition, even if the temperature is rapidly raised and lowered, the IJ- current at the junction between the -n+ [dispersed layer and the p- type substrate] in the source and drain regions remains at the same level as when annealing is performed in a conventional diffusion furnace, which is a problem. There was no.

In the above embodiments, the gate wiring in the MO8 structure was targeted, but the present invention can also be applied to annealing of metal film wiring other than gate wiring, wiring for bipolar semiconductor devices, and general metal film wiring. Furthermore, as the 1-metallic film, in addition to metals or metal silicides, aluminum or its alloys can also be used.

〔Effect of the invention〕

As explained above, 1. In this invention, a furnace with a small heat capacity is used for annealing the metal film wiring, so it does not take time to cool down after annealing, and it is possible to remove the heat from the atmosphere by taking it out from the furnace after cooling down. The negative effects of oxygen and nitrogen can be avoided.

[Brief explanation of the drawing]

Figure 1 is a cross-sectional view showing the main stages of a conventional method for forming metal film wiring, and Figure 2 is a schematic cross-sectional view showing the structure of a conventional diffusion furnace used for annealing. , FIG. 3 is a schematic sectional view showing an example of the structure of an annealing furnace used in the present invention. In the figure, (6a) is a gate wiring (metallic film wiring),
04 is the semiconductor wafer (substrate), 0 o'clock is the chamber, (
Q is a lid for the inlet/outlet of the object to be processed, (17) is a gas inlet, (f) is a gas outlet, and 0 is a heating element. Note that the same reference numerals in the figures indicate the same or corresponding parts. Agent Masuo Oiwa Figure 1 Mr. Commissioner of the Japan Patent Office 1. Description of the case: Japanese Patent Application No. 1982-13'7118 2, Title of the invention: Method of annealing metal film wiring 3, Part 5 to Hitoshi Katayama, representative of the person making the amendment, Detailed explanation of the invention in the specification to be amended. Column 6, Contents of amendment (1) On page 3 of the specification, lines 14 to 16, “By the way, -
[By the way,
2 was conventionally used for annealing to lower the resistance of the gate wiring (6a)." (2) In the same article, page 5, lines 18 to 20, the phrase ``Annealing provides a film resistance of -11111'' was replaced with ``The film resistance decreases due to metal oxides formed during annealing.'' Without any hindrance, a low resistance film with good reproducibility and uniformity can be obtained in this example.

Claims (3)

[Claims] (1) When annealing the metal film wiring formed on the substrate and made of a metal or a conductive compound of the metal, an annealing furnace with a heat capacity of J A method for annealing metal film wiring, characterized in that when taking out the substrate having the metal film wiring, the temperature of the furnace is rapidly lowered, and the substrate is taken out after reaching a low temperature. (2) Claim 1, characterized in that the metallic film wiring is made of a high melting point metal or a high melting point metal silicide.
Annealing method for fully malleable film wiring as described in Section 1. (3) The method of annealing a metal film wiring according to claim 1, wherein the metal film wiring is made of aluminum or an alloy thereof.