JPH03101224A - Low-temperature etching device for semiconductor device - Google Patents
Low-temperature etching device for semiconductor deviceInfo
- Publication number
- JPH03101224A JPH03101224A JP1237235A JP23723589A JPH03101224A JP H03101224 A JPH03101224 A JP H03101224A JP 1237235 A JP1237235 A JP 1237235A JP 23723589 A JP23723589 A JP 23723589A JP H03101224 A JPH03101224 A JP H03101224A
- Authority
- JP
- Japan
- Prior art keywords
- temperature
- semiconductor substrate
- low
- vacuum chamber
- chamber
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 45
- 238000005530 etching Methods 0.000 title claims abstract description 27
- 239000000758 substrate Substances 0.000 claims abstract description 33
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims abstract description 18
- 229910052757 nitrogen Inorganic materials 0.000 claims abstract description 9
- 238000001816 cooling Methods 0.000 claims abstract description 6
- 238000010438 heat treatment Methods 0.000 claims abstract description 4
- 239000011261 inert gas Substances 0.000 claims description 4
- 238000012545 processing Methods 0.000 abstract description 3
- 238000012805 post-processing Methods 0.000 description 9
- 229910045601 alloy Inorganic materials 0.000 description 6
- 239000000956 alloy Substances 0.000 description 6
- 238000010586 diagram Methods 0.000 description 4
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- 239000000460 chlorine Substances 0.000 description 3
- 229910052801 chlorine Inorganic materials 0.000 description 3
- 239000007795 chemical reaction product Substances 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- IFLVGRRVGPXYON-UHFFFAOYSA-N adci Chemical compound C12=CC=CC=C2C2(C(=O)N)C3=CC=CC=C3CC1N2 IFLVGRRVGPXYON-UHFFFAOYSA-N 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
Landscapes
- Drying Of Semiconductors (AREA)
- Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
Abstract
Description
【発明の詳細な説明】 （産業上の利用分野） 本発明は、半導体装置の低温エツチング装置に関する。[Detailed description of the invention] (Industrial application field) The present invention relates to a low temperature etching apparatus for semiconductor devices.
（従来の技術）
近年、半導体装置のエツチング装置では半導体基板を氷
点下に保ったままエツチング（低温エツチング）する装
置が利用されつつある。(Prior Art) In recent years, as etching apparatuses for semiconductor devices, apparatuses that etch semiconductor substrates while keeping them at sub-zero temperatures (low-temperature etching) are being used.
第２図は従来のアルミニウム（ＡＩ）合金膜の低温エツ
チング装置の説明図であって、 １１はエツチング室、
１２は後処理室、１３は搬送室、１４は半導体基板の
受け体、１５は半導体基板の移送部である。FIG. 2 is an explanatory diagram of a conventional low-temperature etching apparatus for an aluminum (AI) alloy film, in which 11 is an etching chamber;
12 is a post-processing chamber, 13 is a transfer chamber, 14 is a receiver for semiconductor substrates, and 15 is a transfer section for semiconductor substrates.
同図において、エツチング室１１において半導体基板（
図示せず）の温度を−１０”Ｃに保ち、Ａ１合金膜の低
温エツチングを行う、この低温エツチングではエツチン
グ反応生成物（ＡｉｌＣｌｌ、）が揮発化せずにＡ１合
金膜の側壁を保護するため、異方性エツチングを実現す
ることができる。 次に半導体基板は、搬送室１３
．移送部１５を経て、後処理室１２に移送され、ａ素プ
ラズマによりレジストや残留塩素の除去処理が施される
。この際。In the figure, a semiconductor substrate (
The temperature of the A1 alloy film (not shown) is maintained at -10"C to perform low-temperature etching of the A1 alloy film. In this low-temperature etching, the etching reaction product (AilCll, ) is not volatilized to protect the side wall of the A1 alloy film. , it is possible to realize anisotropic etching. Next, the semiconductor substrate is transferred to the transfer chamber 13.
．． The film is transferred to the post-processing chamber 12 via the transfer section 15, where it is subjected to resist and residual chlorine removal treatment using a-element plasma. On this occasion.
前記反応生成物（ＡｄＣＩ＋、）中に含まれている塩素
を容易に除去できるように、半導体基板の温度は＋２５
０℃に保たれる。The temperature of the semiconductor substrate was set to +25°C so that chlorine contained in the reaction product (AdCI+) could be easily removed.
It is kept at 0℃.
（発明が解決しようとする課題）
しかしながら、上記の従来技術では、半導体基板の温度
は一１０℃から＋２５０℃に急激に変化するので、半導
体基板や、その上に形成された配線。(Problems to be Solved by the Invention) However, in the above-mentioned conventional technology, since the temperature of the semiconductor substrate changes rapidly from -10°C to +250°C, the temperature of the semiconductor substrate and the wiring formed thereon are extremely low.
絶縁膜に、熱膨張係数の差によるストレスが加わり、結
晶欠陥や配線の断線、あるいは浮き上りが発生するとい
う問題があった。There is a problem in that stress is applied to the insulating film due to the difference in coefficient of thermal expansion, resulting in crystal defects, disconnection of wiring, or lifting.
さらに後処理室１２では最初に半導体基板の温度が上昇
するまでレジストや残留塩素の除去処理が行われず、装
置の制御性に支障をきたしていた。Further, in the post-processing chamber 12, the resist and residual chlorine are not removed until the temperature of the semiconductor substrate rises for the first time, which impairs the controllability of the apparatus.
本発明の目的は、半導体基板の損傷を低減し。An object of the present invention is to reduce damage to semiconductor substrates.
しかも、エツチング処理の制御性の向上が図れる半導体
装置の低温エツチング装置を提供することにある。Moreover, it is an object of the present invention to provide a low-temperature etching apparatus for semiconductor devices that can improve the controllability of etching processing.
（課題を解決するための手段）
上記の目的を達成するため１本発明は、複数の反応室を
有する半導体装置の低温エツチング装置において、前記
反応室の間に半導体基板の温度を制御できる真空室を備
えたことを特徴とする。(Means for Solving the Problems) In order to achieve the above object, the present invention provides a low-temperature etching apparatus for semiconductor devices having a plurality of reaction chambers, in which a vacuum chamber between the reaction chambers can control the temperature of the semiconductor substrate. It is characterized by having the following.
（作 用）
上記手段を採用したため、半導体基板は次の反応室に移
送される前に温度制御されるので、熱膨張係数の差によ
る半導体基板の損傷を回避でき。(Function) By employing the above means, the temperature of the semiconductor substrate is controlled before being transferred to the next reaction chamber, so damage to the semiconductor substrate due to the difference in coefficient of thermal expansion can be avoided.
さらに次の反応室に移送される前に半導体基板の温度を
所定の温度に制御できるので、後処理の制御性の向上が
図れる。Furthermore, since the temperature of the semiconductor substrate can be controlled to a predetermined temperature before being transferred to the next reaction chamber, the controllability of post-processing can be improved.
（実施例） 以下、本発明の実施例を図面に基づいて説明する。(Example) Embodiments of the present invention will be described below based on the drawings.
第１図は本発明の半導体装置の低温エツチング装置をＡ
１合金膜の形成装置に適用した一実施例を示す説明図で
あって、１と２は反応室であって、それぞれエツチング
室と後処理室、３は半導体基板（図示せず）の受け体、
４は搬送室を兼ねたＡｌｌからなる真空室、５は加熱用
のランプヒータ、６は冷却用の窒素導入路、７は半導体
基板の移送部である。FIG. 1 shows a low-temperature etching apparatus for semiconductor devices according to the present invention.
1 is an explanatory diagram showing an embodiment applied to an apparatus for forming an alloy film, 1 and 2 are reaction chambers, respectively, an etching chamber and a post-processing chamber, and 3 is a receiver for a semiconductor substrate (not shown). ,
Reference numeral 4 designates a vacuum chamber made of aluminum that also serves as a transfer chamber, 5 a lamp heater for heating, 6 a nitrogen introduction path for cooling, and 7 a transfer section for semiconductor substrates.
同図において、半導体基板の移送部７は、エツチング室
１では第２図で説明した公知の処理が施され１次に冷却
用の窒素によって予め一１０℃に温度制御されている真
空室４に移送され、ランプヒータ５によって十分長い時
間（５分程度）をがけて＋２５０℃まで昇温される。こ
の後、半導体基板は後処理室２に移送されて、第２図で
説明した公知の処理が施される。In the same figure, the semiconductor substrate transfer section 7 is transferred to the etching chamber 1 where the known process explained in FIG. The temperature is increased to +250° C. by the lamp heater 5 over a sufficiently long time (about 5 minutes). Thereafter, the semiconductor substrate is transferred to the post-processing chamber 2 and subjected to the known processing described in FIG. 2.
また前記真空室４は半導体基板が後処理室２に移送され
た後１次の半導体基板に備えて再び冷却用の窒素によっ
て予め−ｌＯ℃に降温させられる。Further, after the semiconductor substrate is transferred to the post-processing chamber 2, the temperature of the vacuum chamber 4 is lowered to −10° C. again by cooling nitrogen in preparation for the first semiconductor substrate.
真空室４は容易に昇温または降温できるように熱容量の
小さなＡｍなとで構成されている。The vacuum chamber 4 is constructed of Am having a small heat capacity so that the temperature can be easily raised or lowered.
また移送部７は各反応室１，２と真空室４を断熱するた
めに熱容量の大きなセラミックスなどで構成されている
。Further, the transfer section 7 is made of ceramics or the like having a large heat capacity in order to insulate each reaction chamber 1, 2 and the vacuum chamber 4 from each other.
以上のように本実施例によれば、反応室１，２の間に半
導体基板の温度を制御できる真空室４を備えたことによ
り、半導体基板は冷却用の窒素と加熱用のランプヒータ
５によって十分に長い時間をかけて一１０℃から２５０
℃まで昇温されるので、熱膨張係数の差による半導体基
板の損傷を防止できる。さらに半導体基板の温度は後処
理室２に入る前に、既に真空室４で２５０℃まで上昇さ
れているので後処理の制御性を向上させることができる
。As described above, according to this embodiment, since the vacuum chamber 4 that can control the temperature of the semiconductor substrate is provided between the reaction chambers 1 and 2, the semiconductor substrate is heated by the nitrogen for cooling and the lamp heater 5 for heating. Heat from -10℃ to 250℃ for a sufficiently long time.
Since the temperature is raised to .degree. C., damage to the semiconductor substrate due to differences in thermal expansion coefficients can be prevented. Furthermore, since the temperature of the semiconductor substrate is already raised to 250° C. in the vacuum chamber 4 before entering the post-processing chamber 2, the controllability of the post-processing can be improved.
また窒素以外の不活性ガスを真空室４に導入して、上記
の温度制御を行ってもよく、さらに受け体３を窒素や不
活性ガスで冷却することで温度制御を行うことも考えら
れる。Further, the above temperature control may be performed by introducing an inert gas other than nitrogen into the vacuum chamber 4, and it is also conceivable to perform temperature control by cooling the receiver 3 with nitrogen or an inert gas.
なお、上記の実施例ではＡｆｆ合金膜の低温エツチング
装置の例を示したが、多結晶シリコン膜や高融点シリサ
イド膜などのエツチングの場合にも利用できる。In the above embodiment, an example of a low-temperature etching apparatus for an Aff alloy film is shown, but the present invention can also be used for etching a polycrystalline silicon film, a high melting point silicide film, or the like.
また真空室４は反応室の１種としても利用できる。Further, the vacuum chamber 4 can also be used as a type of reaction chamber.
（発明の効果）
本発明によれば１反応室の間に半導体基板の温度を制御
できる真空室を備えたことにより、半導体基板の損傷を
低減でき、エツチング処理の制御性が高精度に行える半
導体装置の低温エツチング装置を提供できる。(Effects of the Invention) According to the present invention, by providing a vacuum chamber in which the temperature of the semiconductor substrate can be controlled between one reaction chamber, damage to the semiconductor substrate can be reduced and the etching process can be controlled with high precision. A low-temperature etching device can be provided.
第１図は本発明による半導体装置の低温エツチング装置
の一実施例を示す説明図、第２図は従来の半導体装置の
低温エツチング装置を示す説明図である。
１．２・・・反応室、 ３・・・受け体、 ４・・・真
空室、 ５ ・・・ランプヒータ、 ６・・・窒素導入
路、 ７ ・・・移送部。FIG. 1 is an explanatory diagram showing an embodiment of a low-temperature etching apparatus for semiconductor devices according to the present invention, and FIG. 2 is an explanatory diagram showing a conventional low-temperature etching apparatus for semiconductor devices. 1.2...Reaction chamber, 3...Receptor, 4...Vacuum chamber, 5...Lamp heater, 6...Nitrogen introduction path, 7...Transfer part.
Claims (4)
グ装置において、前記反応室の間に半導体基板の温度を
制御できる真空室を備えたことを特徴とする半導体装置
の低温エッチング装置。(1) A low-temperature etching apparatus for semiconductor devices having a plurality of reaction chambers, characterized in that a vacuum chamber capable of controlling the temperature of the semiconductor substrate is provided between the reaction chambers.
の搬送室を兼ねることを特徴とする請求項（１）記載の
半導体装置の低温エッチング装置。(2) The low-temperature etching apparatus for semiconductor devices according to claim (1), wherein the vacuum chamber also serves as a transfer chamber for transferring semiconductor substrates between reaction chambers.
求項（１）記載の半導体装置の低温エッチング装置。(3) The low-temperature etching apparatus for semiconductor devices according to claim (1), wherein the vacuum chamber also serves as a reaction chamber.
窒素や不活性ガスの真空室への導入、または窒素や不活
性ガスによる半導体基板の受け体の冷却によって行うこ
とを特徴とする請求項（１）記載の半導体装置の低温エ
ッチング装置。(4) A claim characterized in that the temperature control in the vacuum chamber is performed by lamp heating, introducing nitrogen or an inert gas into the vacuum chamber, or cooling the semiconductor substrate receiver with nitrogen or an inert gas. (1) A low-temperature etching apparatus for a semiconductor device according to the above.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23723589A JP2592682B2 (en) | 1989-09-14 | 1989-09-14 | Low temperature etching equipment for semiconductor devices |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23723589A JP2592682B2 (en) | 1989-09-14 | 1989-09-14 | Low temperature etching equipment for semiconductor devices |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH03101224A true JPH03101224A (en) | 1991-04-26 |
| JP2592682B2 JP2592682B2 (en) | 1997-03-19 |
Family
ID=17012391
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP23723589A Expired - Fee Related JP2592682B2 (en) | 1989-09-14 | 1989-09-14 | Low temperature etching equipment for semiconductor devices |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2592682B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR970003600A (en) * | 1995-06-29 | 1997-01-28 | 김주용 | Low Temperature Etching Method |
| KR20190142107A (en) * | 2018-06-15 | 2019-12-26 | 삼성전자주식회사 | Method of etching in low temperature and plasma etching apparatus |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6027129A (en) * | 1983-07-25 | 1985-02-12 | Mitsubishi Electric Corp | Method for annealing metallic film wiring |
| JPS62193099A (en) * | 1986-02-20 | 1987-08-24 | 富士通株式会社 | Vacuum chamber |
| JPS6421926A (en) * | 1987-07-17 | 1989-01-25 | Hitachi Ltd | Low temperature dry etching apparatus |
-
1989
- 1989-09-14 JP JP23723589A patent/JP2592682B2/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6027129A (en) * | 1983-07-25 | 1985-02-12 | Mitsubishi Electric Corp | Method for annealing metallic film wiring |
| JPS62193099A (en) * | 1986-02-20 | 1987-08-24 | 富士通株式会社 | Vacuum chamber |
| JPS6421926A (en) * | 1987-07-17 | 1989-01-25 | Hitachi Ltd | Low temperature dry etching apparatus |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR970003600A (en) * | 1995-06-29 | 1997-01-28 | 김주용 | Low Temperature Etching Method |
| KR20190142107A (en) * | 2018-06-15 | 2019-12-26 | 삼성전자주식회사 | Method of etching in low temperature and plasma etching apparatus |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2592682B2 (en) | 1997-03-19 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |