JPS6027186B2 - semiconductor equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and in particular to an SOS (Silicon
ohSapphire) structure MOS integrated circuit.

As shown in FIG. 1, which shows a cross-sectional view of the process of forming an aluminum electrode pattern, this type of semiconductor device is designed to cover a silicon layer 2 formed in an island shape on an insulating substrate 10 such as single-crystal saphia. An oxide film 1 is formed on the entire surface, an aluminum vapor deposition layer 4 is formed on this, and this is patterned using a photosensitive resin 5.

Bonding for external connection to the patterned aluminum electrode (wiring) layer is performed on a part other than the silicon layer 2 on the insulating substrate, so that the bonding line is connected to the external part of the aluminum layer. Failures such as peeling or peeling of the connected portion from the insulating substrate 10 occurred frequently.

The reason for this is that the insulating substrate 10 and the external connection part of the aluminum layer are in contact with each other only through the oxide film 1, and as a result, the external connection part lacks flexibility and the connection strength with the bonding wire is reduced. This is because the size is small, and the adhesion strength between the external connection portion and the substrate 10 is low. moreover,
The thickness of the vapor deposited aluminum layer 4 and the coating thickness of the photosensitive resin 5 tend to become thinner at the stepped portion 3 formed by the island-like silicon layer 2, and as a result, the photosensitive resin coating 5 is eroded during the aluminum etching process, resulting in pinholes. In many cases, the aluminum electrode was side-etched and cut off.

In the aluminum evaporation process, the evaporation source for the aluminum evaporation layer is a multi-point source, the substrate holder is precessed to deposit from a wide solid angle, and the photosensitive resin is applied using the conventional spin coating method. (Using a spray coating method to gently fill in the differences in level improved this to some extent, but it was not sufficient as there was insufficient exposure at the differences in level.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device with an SOS structure that prevents peeling of bonding lines and peeling of metal interconnections connected to the outside.

The present invention is characterized in that a semiconductor layer is interposed between the external connection portion of the metal wiring and the insulating substrate.

Due to this intervening semiconductor layer, the connection portion of the metal wiring with the outside has some elasticity, and as a result, the bonding wire can be connected well and the connection strength is improved.

Furthermore, the adhesion strength between the external connection portion and the insulating substrate is also improved. Furthermore, the intervening semiconductor layer also has the advantage of making it easier to align masks for forming wiring patterns.Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 3 is a plan view showing one embodiment of the present invention, and FIG. 2 is a cross-sectional view taken along line C--○ in FIG. 3, showing the order of manufacturing steps.

That is, the silicon layer formed on the insulating substrate 10 is selectively etched to remove the silicon layer 2 that is to be located under the island-shaped silicon layer 2 where the device is to be formed and the connection portion with the outside of the metal wiring described below. 2' is formed. After a device region is formed on the island-shaped silicon layer 2, the surface is covered with an oxide film 1, and a contact hole for the device region is formed in this. Then, the aluminum layer 4 is deposited. After aluminum evaporation, silicon oxide film 6 is grown in low temperature vapor phase.
It is deposited on the aluminum layer 4 by high frequency sputtering, electron beam evaporation, etc. (FIG. 2A). After selectively etching the silicon oxide film 6 with ammonium fluoride buffer solution at room temperature by photolithography, the aluminum layer 4 is etched with 70 to 90 oo of concentrated phosphoric acid using the silicon oxide film 6 as a mask. The formation temperature of the silicon oxide film 6 used in this step is such that the aluminum evaporation film 4 reacts with the silicon oxide film 1 directly below the aluminum evaporation film 4, reducing the insulation resistance and impairing the etching properties of the aluminum 4. It is necessary to keep it below 300oo to avoid
Even if the components change to some extent and become conductive, it remains only directly above the aluminum wiring 4, so it does not affect the characteristics. Since this Sea J-con oxide film 6 is formed at a low temperature, the etching rate is extremely high, and the photosensitive resin is not corroded to cause pinholes.

Moreover, it is hardly attacked by phosphoric acid, so the side etching of aluminum 4 is 4. The silicon oxide film 6 directly above the connecting portions 7', 7'' of the aluminum wirings 4', 4'' thus formed with the external leads is again etched away by photolithography to complete the process (FIG. 2B). Connection part 7
Since the elastic silicon layer 2 is interposed between the wires 7' and 7" and the insulating substrate 10, the bonding strength between the bonding wires leading to the external leads and the connection portions 7' and 7" is increased. , the adhesion strength between the wiring portions 7', 7'' and the substrate 10 is improved.

Furthermore, the presence of the silicon layer 2' has the advantage of facilitating mask alignment in the photoresist process.

[Brief explanation of the drawing]

Fig. 1 is a cross-sectional view showing the aluminum etching process of a conventional SOS-MOS integrated circuit, Figs. 2 and 3 are examples of applying the present invention to an SOS-MOS integrated circuit, and Fig. 3 shows the completed state. 2A and B' show the cross-sectional views along C-C' in the order of steps. 1... Oxide film, 2... Silicon, 3... Step portion, 4...
・...Aluminum vapor deposited film, 5...Photosensitive resin, 6...
. . . Silicon oxide film, 10 . . . Single crystal sapphire, 7 . . . Connection portion. Figure 1 Figure 2 'A' Figure 2 'a' Figure 3

Claims (1)

[Claims] 1. In a semiconductor device in which an element region is formed in an island-shaped semiconductor layer on an insulating substrate, and a metal wiring led out from this element region is formed extending on the insulating substrate, the metal wiring layer is connected to the outside of the metal wiring layer. A semiconductor device characterized in that a semiconductor layer is interposed between a connecting portion of the insulating substrate and the insulating substrate.