JPS6028022B2 - input/output processing unit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an input/output processing device that controls data transfer between an input/output device and a main memory via an input/output channel.

In a centralized control input/output channel, the data buffer and registers for storing control information are RAM.
etc., and are configured in a concentrated manner in terms of hardware, and a pipeline method is often sought to access this.

The data buffers etc. in parentheses are accessed from both the channel (input/output interface control unit) side and the memory data transfer control unit side, so when access from one control unit occurs, access from the other side is disabled. It needs to be banned for a certain period of time. Conventionally, when an access request is issued from a memory data transfer control unit, acceptance of the access request from the channel side is completely prohibited, and the flow of the pipeline is temporarily stopped. This creates idle time in the access processing cycle, which increases the waiting time for access requests from the channel, which is a factor that reduces the processing capacity of the processing device. An object of the present invention is to provide an input/output processing device that increases the processing capacity of the entire device by reducing the idle time of access cycles as much as possible without stopping the flow of pipeline access to the data buffer, etc. There is a particular thing.

The present invention accesses the register memory that stores information corresponding to a plurality of channels, such as the data buffer and the control register, in a pipeline manner, and accesses the register in parentheses (for example, controls data transfer with the memory). When an access request occurs from a circuit that controls the control unit, out of the access requests from multiple other channels, only the access request for the corresponding channel (which one of the control units is trying to access) is prohibited for a certain period of time, and the other It is characterized by accepting access requests from channels.

FIG. 1 is a block diagram showing a portion of the input/output processing device related to the present invention. Reference numeral 1 denotes a memory data transfer control unit that controls data transfer between the input/output processing device and the main memory.

2 to 5 are input/output channels that control data transfer with input/output devices via input/output interfaces.

From these input/output channels, control information register 15
When an access request is made to the access request signal 101-1
04 to '11'.Access request signals 101 to 104 are sent to access permission gates 10 to 104.
13 to the channel access selection circuit 14 and accesses the control information register 15. The control information register 15 stores information necessary for controlling data transfer for each channel. This includes, for example, the number of valid data in a data buffer (not shown). Every time data is transferred between the data buffer and the input/output device, the channel accesses the control information register 15, reads the corresponding information, and sets the number of valid data to the required number (the number of transferred data). ) and then write it again. This control register 15 is generally RA
M, etc., and is accessed by pipeline control to increase access speed. FIG. 2 shows the time relationship of this pipeline system. In this embodiment, the read cycle (READ), the modification cycle (M
○It is divided into three types of cycles: D and Y cycle, MOD cycle), and write cycle (WRITE cycle).
These cycles flow in a pipeline manner, and access requests are processed one cycle at a time. In Figure 2, when processing of an access request from channel A begins, READ
, A cycle, information corresponding to channel A is extracted from the information register 15 in FIG.
is immediately set. In the next MOD, A cycle, the contents of the read register 16 are changed by the modification circuit 17 as necessary. Further, the information changed in the next WRITE, A cycle is stored again in the corresponding field of the information register 15. Subsequent access requests from other channels are also processed cycle by cycle, and one access is processed in three cycles, but each cycle is processed seamlessly, so in total only one access is processed per cycle. The request can be processed. Now, the memory data transfer control unit 1 in FIG. 1 also needs to access the information register 15. For example, when data transfer between the main memory and the data buffer is completed, it is necessary to increase or decrease the number of valid data. This access request is instructed by the memory control unit access signal 105. When an access request occurs from this memory data transfer control unit 1,
It is necessary to temporarily suspend the processing of access requests from the channel. One reason is that only one access to the information register 5 can be processed per cycle, so naturally the processing of access requests for all channels is interrupted for at least one cycle, and memory data is not processed in the flow of the pipeline. It is necessary to insert one cycle for processing the access request of the transfer control unit 1. Another reason is the need to guarantee the temporal ordering of changes in the contents of the information registers. In FIG. 2, the access request from the memory data transfer control unit 1 is started from cycle number 4.
, WRITE ○ are processed in each cycle. In this access request, the contents of the field corresponding to channel D are read and changed. in this case,
For example, it is not possible to start processing an access request for channel D from input/output channel 5 in cycle number 2. This is because if cycle number 2 and input/output channel 5
When performing a READ cycle for channel D from
The WRITE cycle is executed in cycle number 4, which overlaps with the READ cycle of the access request from the memory data transfer control unit 1. This means that the information being written is read out, and the order of the information is reduced. Also, in cycle number 6, an access request from input/output channel 5 of channel D must not be started. In this case, the output of information by channel D and the writing to the same field by an access request from memory data transfer control unit 1 overlap. That is, during the period from cycle numbers 2 to 6, it is necessary to prohibit processing of access requests from channel D, and conversely, processing of other channels should be performed. It can be seen that the waveform indicated by 109 in FIG. 2 prohibits access requests from channel D during the period from cycle numbers 2 to 6. Returning to FIG. 1, reference numerals 6 to 9 are channel-based access request permission flip-flops, and these flip-flops are set and reset by the memory data transfer control section 1.

In the above example, the flip-flop 9 corresponding to channel D is reset during cycle numbers 2-6. The outputs of flip-flops 6-9 are sent as channel-specific access permission signals 106-109 to corresponding channel access permission gates 10-13, respectively. The memory data control unit 1 further sends out a channel access permission signal 110.

This is a signal that prohibits access to all channels since the memory data control unit 1 itself accesses it, and the waveform indicated by 110 in FIG. 2 becomes "0" only during cycle number 4. This signal is sent to all of the access permission gates 10-13. Access request signals 101 to I04 from each channel are transmitted to access permission gate 1.
0 to 13 are ANDed, and the output signal is sent to the channel access selection circuit 14. The channel access selection circuit 14 selects one of these four access requests every cycle to access the information register 15. According to the present invention, a register that stores information corresponding to a plurality of channels constituted by a RAM, etc.
The pipeline system guarantees the order of changes in information required when accessing from multiple channels and other control units, and also improves the performance of the input/output processing device by making registers accessible without breaks. Improve.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a time chart explaining FIG. 1. 1...Memory data transfer control unit, 2-5...
...Input/output channels, 6 to 9...Channel-specific access request permission flip-flops, 10 to 13...
- Access permission gate, 14... Channel access selection circuit, 15... Information register group, 16.
...Proposal register, 17...Modification circuit. Figure 1 Figure 2

Claims (1)

[Claims] 1. In an input/output processing device that controls data transfer between an input/output device and main memory via an input/output channel,
A register group means that stores information for each channel and executes read, change, and write cycles in a pipeline manner, and an access request to the register group means based on data transfer between the input/output device and the input/output device. a first control means for controlling; a second control means for controlling an access request to the register group means based on data transfer with the main memory; and information regarding an input/output channel in the second control means. When an access request for the input/output channel occurs, each of the read, change, and write cycles due to the access request from the first control means regarding the input/output channel is the read, change, and write cycle by the second control means. The access request from the first control means regarding the input/output channel is prohibited for a predetermined cycle so as not to overlap with the access request from the first control means regarding the input/output channel, and the access request regarding the entire input/output channel is prohibited during the read cycle by the second control means. 1
1. An input/output processing device comprising: means for prohibiting access requests from a control means.