JPS6028255A - Semiconductor device - Google Patents

Abstract

PURPOSE:To improve the density of mounting easily by respectively fitting chips, chip selective logics thereto differ to each other, to the surface and back of a molding ribbon so as to be mutually arranged in symmetrical manner regarding the position of a junction pad. CONSTITUTION:A ROM chip 100 is fixed to an island 500 in the surface A of a molding ribbon and wired 200, and a ROM chip 300 is set to an island 600 in the surface B and wired 400. Since both surfaces are arranged in symmetrical manner while using X-Y lines as axes, all pins are connected in common through a resin seal, thus obtaining a ROM, capacitance thereof is magnified in double. The areas of the island sections can be reduced, a connection is simplified, and a device having the high density of mounting is acquired.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a semiconductor device that can improve the packaging density of semiconductor integrated circuits.

(Prior Art) As one means for increasing the functionality of a semiconductor device, a through-mounting method in which a plurality of chips are mounted in the same package has been put into practical use. In these devices, the signal terminals in many cases have independent functions, except for terminals such as power supply pins, so even if these chips are housed in the same package, special wiring for the terminals is required. No ingenuity required 0 In other words, the total number of terminals (number of bonding pads) of the chips stored in one package and the total number of terminals (number of bins) of the package itself are set to be approximately the same. This is because

On the other hand, in devices such as memory devices in which input terminals, output terminals, etc. are used in a commonly connected state for their functions, there are very few terminals that require mutually independent functions.

FIG. 1 is a diagram for explaining this, and shows a state where two bits ROMI and ROM2 are used on the memory board from the top surface of the board. The ROM device in this example is composed of 24 bins, and the chip select function is provided in the 20th bin.

1 to 24 in the figure are pin terminal numbers. l), Ao
-Adz is the atsis input terminal, Do-D7 is the output terminal,
Vcc is a power supply terminal, and Vss is a ground terminal.

As you can see from this Figure 1, these two ROM1,
ROM device of ROM2 is chip select terminal -C8
(pin 20) are all connected in common.

That is, the total number of terminals of the ROM is 24×2, 48, but when two ROM devices are viewed as one device, only 25 terminals are required. In this example, two bit ROMs are used for 64, and the number is set to 128)
The 0 chip select terminal C8 used as a ROM is for controlling the signal output from the output terminal of the ROM, and the ROM is activated or deactivated by inputting rHJ level or "L" level. becomes. Which logic level to set is determined at the chip design stage depending on the application.

The ROM device in Figure 1 has a chip select logic level r
Assuming that it is designed to be active at LJ,
When reading the sound from the memory contents of ROMI, input the chip select terminal K rLJ level of ROM1, and read the sound from the ROM2 memory.
The rHJ level is input to the chip select i.

By doing this, the ROMI is not in an active state and the output terminal is activated in response to the address input signal.

ROM data is output to D7. At this time, the ROM
2 is in the inactive state, so its output terminal is −
Since D is maintained in a high impedance state, ROM data is not output even if an address input signal is input.

Conversely, the ROMI chip select terminal has “H” level, R
When the ILJ level is input to the chip select terminal of OM2, contrary to the above, the data of ROM'2 is output and the data of ROMI is not output.

As shown in the figure, the highest address of the ROM is the address input terminal A12, but for the above reason, by using the chip select terminal as All, by using two bit ROMs in the 64, the highest address of the ROM is the address input terminal A12. It can be used as a bit ROM.

This method is generally used when expanding the capacity of a memory device.

From these facts, it can be seen that in order to double the storage capacity by using two ROM devices, the following conditions need to be met.

(1) The input terminal, output terminal, power supply terminal, and ground terminal are all connected in common.

(2) When one ROM is active, the other ROM is inactive.

By the way, the most efficient way to double the capacity using two chips is to simultaneously store the two chips in one package.

Currently, the most widely used LSI packaging method is to fix the chip on one side of a patterned thin metal plate called a mold ribbon as shown in Figure 2, perform wire bonding, and then apply mold resin to the metal plate. This is a method of pouring and shaping using a mold.

If two memory chips are to be housed in one package using this conventional method, the following disadvantages arise.

(1) Since the chip is fixed only on one side of the mold ribbon, the area of the island portion (the area where the chip is fixed) must be at least twice as large as that for storing one chip.

(2) For the same reason as in item (1), common wiring (wire bonding) for terminals is extremely complicated and practically impossible.

(3) To avoid the disadvantage of (2), a special molded ribbon with complex patterning is required.

(Object of the Invention) This invention was made to eliminate the above-mentioned conventional drawbacks, and it is possible to easily store two chips in one package by using the same or almost the same mold ribbon as in the case of storing a single chip. An object of the present invention is to provide a semiconductor device that can store a ROM chip, has a small island portion area, and can be easily wire bonded.

(Structure of the Invention) In the semiconductor device of the present invention, chips having different chip select logics are loaded on both the front and back surfaces of a mold ribbon so as to be mirror-symmetrical with respect to the positions of the bonding pads.

(Embodiments) Hereinafter, embodiments of the semiconductor device of the present invention will be described based on the drawings.

FIG. 3 is a diagram for explaining the position of wire bonding pads of a ROM chip used in one embodiment. Hereinafter, one side of the mold ribbon will be referred to as side A, and the opposite side will be referred to as side B. FIG. 3(a) shows a chip fixed on the A side, and FIG. 3(b) shows a chip fixed on the B side, both of which are views from the top of the chip.

The numbers in FIGS. 3(a) and 3(b) represent the bin numbers to which the respective pads are connected. As you can see from this figure, the memory chip fixed on the A side (hereinafter referred to as A
The bonding pad positions of the memory chip (hereinafter referred to as the 8-sided chip) fixed on the B side (hereinafter referred to as the 8-sided chip) are
- It is designed to have mirror symmetry with the Y line as the axis of symmetry.

Furthermore, the logic level of the chip select terminal of the A-side chip is designed in advance to be rLJ, and the logic level of the chip select terminal of the B-side chip is designed in advance to be rHJ.

FIG. 4(a) shows the A-side chip 100 on the mold ribbon.
It is a view seen from the A side after wire bonding is performed with wire wire 200 after fixing to the surface.

In addition, FIG. 4(b) shows that after that, 3
FIG. 3 is a view seen from side B after fixing the surface chip 300 and performing wire bonding with wire wires 400. Note that 500 in FIG. 4(a) and 600 in FIG. 4(b) each indicate an island portion.

As can be seen from FIGS. 4(a) and 4(b), both of them, including the chip, are mirror-symmetrical with the XY line as the axis of symmetry. Thereafter, as described above, when molding is performed using a metal mold, a ROM with double the capacity in which all the bins are connected in common is produced.

In this embodiment, the chip select bin is also commonly wired, but as mentioned above, the chip select logic for the A-side chip and the B-side chip is designed with reverse logic, so the commonly connected chip select terminal is A13 ( i.e. 128K
Even if it is used as the highest address of the ROM, there will be no problem in operation.

Although the 64KROM used in this example has only one chip select terminal, even in memory devices with multiple chip select terminals, the chip select terminal used as the highest address when the capacity is doubled is used. The above object can be achieved by preparing two chips whose chip select logics are designed to be opposite to each other.

Further, in this embodiment, a ROM device has been described, but it goes without saying that similar effects can be expected in a RAM device as well.

(Effects of the Invention) As described above, according to the semiconductor device of the present invention, chips with different chip select logics are loaded on both the front and back sides of the mold ribbon so that they are mirror symmetrical with respect to the positions of the bonding pads. Two ROM chips can be easily housed in one package using the same or almost the same molded ribbon as for a single chip, increasing the memory device capacity multiple times and reducing the island area. The number of wires can be reduced, and wire bonding can be easily performed.

[Brief explanation of the drawing]

Figure 1 is a wiring diagram between each terminal of a memory board on which two conventional 64K ROMs are mounted, Figure 2 is a plan view of a molded ribbon used in an embodiment of the semiconductor device of the present invention, and Figure 3 (a).
) and FIG. 3(b) are diagrams showing the positions of the bonding pads of two chips used in one embodiment of the semiconductor device of the present invention, and FIG. 4(a) and FIG. 4(b) are respectively FIG. 2 is a plan view of a mold ribbon used in the semiconductor device of the present invention, with chips assembled on both sides thereof. 100...A-side chip, 200, 400...wire, 300...B-side chip, 500,600...
Island part.

Claims (1)

[Claims] A semiconductor device characterized in that chips having different chip select logics are loaded on both the front and back sides of a mold ribbon so that they are mirror symmetrical with respect to the positions of bonding pads.