JPS6028338A - Address controller of elastic memory - Google Patents

Abstract

PURPOSE:To prevent an error or out of synchronism from being caused at address control by adding a signal produced from a write address to an external clock when both read and write addresses approach a prescribed difference to use the controller for the constitution of a synchronism network and complete suppression of jitter in PCM communication. CONSTITUTION:A write clock CLKIN is fed to a write address generating counter 2 to give a write address 5 of a data input DATAIN to a memory 1 and a read clock CLKOUT obtained from a PLL9 is fed to a read address generating counter 3 to give a read address 6 of a data output DATAOUT to the memory 1. When the difference between the read address 6 and the write address 5 reaches a prescribed value, it is detected by an address comparison detection section 4a and an output of an asynchronous presettable synchronism counter 8 is preset to the same value as an output of the write address generating counter 2 by using a load signal 7a. Thus, the PLL9 compares tentatively the read address 6 and the write address 5 and both the addresses are separated continuously.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to an elastic memory address control device used for synchronous network configuration, jitter suppression, etc. in PCM communication.

[Background of the invention]

A conventional elastic memory address control device used in PCM communication to configure a synchronous network and completely suppress jitter has a configuration as shown in the block diagram of FIG. 1, for example. In FIG. 1, 1 is an IJ, 2 is a write address generation counter, 6 is a read address generation counter, 4 is an address comparison control section 5 is a write address, 6 is a read address, 7 is an address control signal, and DATA IN is a write address generation counter. Data input, DATA OUT
is data output, CLKIN is write clock, EXTC
LK is an external clock, and CLKOUT is a read clock. FIG. 2 is an address control time chart illustrating temporal changes in the write address 5 and read address 6 shown in FIG.

In a conventional device with such a configuration, the write clock CLK
, the write address 5 of the memory 1 generated by the write address generation counter 2 by IN and the external clock EXTCL.
When the read address 6 generated by the read address generation counter 3 approaches a certain difference due to K, the read address generation counter 3 is controlled by the address control signal 7 from the address comparison control section 4, and the read address 6 is changed to the value shown in FIG. The method used was to fly from point A to point B. Therefore, at this time, there are drawbacks such as errors in the data and furthermore, loss of synchronization on the receiving side.

[Purpose of the invention]

The purpose of the present invention is to eliminate the above-mentioned drawbacks of the prior art, and to
An object of the present invention is to provide an elastic memory address control device which is used for synchronous network configuration and complete jitter suppression in CM communication and does not cause errors or out-of-synchronization during address control.

[Summary of the invention]

The present invention provides an elastic memory consisting of both address counters for writing and reading, a memory, and an address comparison control section. An asynchronous presettable synchronous counter is provided, and a PLL is used to prevent errors or out-of-synchronization when separating both addresses.
Since it is necessary to compare the read address and write address at the same time as comparing the read clock of the LL output, normally P
The read clock of the LL output is compared with the external clock, and when the read and write addresses approach a certain difference, the write address is added to the external clock to achieve the above purpose. It is a control device.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to FIGS. 6 and 4.

FIG. 6 is a configuration block diagram showing an embodiment of an elastic memory address control device according to the present invention, in which the same reference numerals as in FIG. 1 indicate the same or corresponding parts,
4a is an address comparison detection section, 7a is a load signal, 8 is an asynchronous presettable synchronous counter, 9 is a PLL, 10 is a reference signal, and 11 is a comparison signal. FIG. 4 is an address control time chart of FIG. 6.

To explain the operation of the configuration shown in FIG. 3, first, the write clock CLKIN is input to the write address generation counter (CNT
W) Added to 2 and data input DATAIN to memory 1
At the same time, the read clock CLKOUT obtained from the output of the PLL 9 is applied to the read address generation counter (CNTR) 3, and the read address 6 of the data output DATAOUT is provided to the memory 1. At this time, the external clock EXTCLK is applied to the asynchronous presettable synchronous counter (CNTE) in the same frequency dividing stage as the read address generation counter (CNTR) 3, and its output is
It is used as the reference signal 10 of the LL9, and the output of the read address generation counter (CNTR) 3 is used as the comparison signal 11 of the PLL9. As a result, the same normal operation as that of the conventional elastic memory address control device as illustrated in FIG. Address comparison detection section (ADDET) 4
a, and the load signal 7a presets the output of the asynchronous presettable synchronous counter (CNTE) 8 to be the same as the output of the complimentary address generation counter (CNTW) 2. This corresponds to point A in FIG. As a result, the PLL 9 temporarily compares the read address 6 and the write address 5, and continuously separates both addresses. This corresponds to between point A and point B in FIG.

If the device of this embodiment is used for synchronous network configuration of PCM communication or complete jitter suppression in this way, it will be a mistake! This makes it possible to prevent the occurrence of errors or loss of synchronization on the receiving side.

〔Effect of the invention〕

As described above, according to the elastic memory address control device of the present invention, in order to configure a synchronous network and completely suppress jitter in PCM communication, even when reading is performed using an external clock that is completely independent of the write clock. This has the advantage that it is possible to prevent errors and out-of-synchronization on the receiving side that would otherwise occur due to the separation of both write and read addresses, and it is possible to easily realize a circuit configuration of an elastic memory with excellent performance.

[Brief explanation of drawings]

FIG. 1 is a configuration block diagram illustrating a conventional elastic memory address control device, FIG. 2 is an address control time chart of FIG. 1, and FIG. 3 is an implementation of the elastic memory address control device according to the present invention. A configuration block diagram showing an example, FIG. 4 is an address control time chart of FIG. 6. 1... Memory 2... Write address generation counter 6... Read address generation counter 4a... Address comparison detection unit 5... Write address 6... Read seat address 7a... Load signal 8. ...Asynchronous presettable synchronous counter 9...PLL 10...
Reference signal 11... Comparison signal foil 17 Mo2 figure drop 3V O^TAIIJ- Sugar 4z

Claims (1)

[Claims] a memory, both address counters for writing and reading of the memory, an address comparison detection section that compares and detects the outputs of the two address counters, and an asynchronous presettable that controls the read address counter with the output of the address comparison detection section. An elastic memory address control device consisting of a synchronous counter.