JPS6029059A - Digital/analog converter - Google Patents

Abstract

PURPOSE:To prevent the output distortion due to the capacitance difference between a capacitor from occurence without increasing a conversion time by charging alternately two capacitors by a control circuit responding to a digital input to hold the charge at a holding circuit respectively. CONSTITUTION:The switches 1, 2 and 6 are controlled by the control circuit 10 of a D/A converter, and the capacitors C1 and C2 are charged with a reference voltage plus V responding to the digital input. The charge which charged the capacitors C1 and C2 are held in respective holding circuits 4 and 8 by the control of the switches 2, 3 and 7. The adder 9 adds the output of the circuits 4 and 8, and outputs analog signals. Without increasing the conversion time, the output distortion the due to capacitance differences between the capacitors C1 and C2 is prevented from occurence.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a digital-to-analog converter (hereinafter referred to as a D/A converter). , especially the charge redistribution method I)/
Regarding A converter.

One type of D/A converter for converting a binary digital signal of a predetermined number of bits into an analog signal is a so-called charge redistribution type converter.

FIG. 1 is a circuit block diagram of an example of a D/A converter using this charge redistribution method, in which a capacitor C1 and a second capacitor C1 of equal capacitance each have one end connected to a predetermined reference potential point (for example, ground). and C2 are provided, and control such as charging and discharging of these capacitors is performed by on/off operations of the switch elements 1 to 3.

Specifically, a switch 1 is provided to control the charging of the capacitor C, and a switch 2 is provided to control the redistribution of the charge in the capacitor C1 to the capacitor C2. A switch 3 is provided to discharge and reset the charge of the capacitor C1, and each of these switches 1 to 3 receives a control signal (A) generated from a control circuit 5 in response to a digital input signal (A). B
) to (D) are respectively on/off controlled. The charge charged in the second capacitor c2 at the end of a series of digital input signals of a predetermined focus is sampled and held in the sample and hold circuit 4, and the output of this hold becomes an analog signal corresponding to the digital input signal. Figure 3 shows the digital signal (A
) is a diagram showing the timing of control signals (B) to (D) with respect to FIG. Figure 2 shows the case where the predetermined bit of the digital input signal (A) is "i", and Figure 3 shows the case where the predetermined bit of the digital input signal (A) is "o".
”.

Referring to Figure 2, the bit sign of the input signal is shown in Figure (A).
In the case of 1'', the control signal (B) is first at a high level for a predetermined period, turning on the switch 1.

During this time, the capacitor C1 is charged to have a charge of Ql-C1.V (]). Note that ■ is the charging voltage.

After that, the control signal (C) becomes high level for a predetermined period of time, turning on the switch 2. At this time, if the capacitor C2 is already charged with a charge C6, the switch 2
The new charge Q2 of capacitor C2 is redistributed by turning on Q2.
is C2-(C2/(C1+C2 month)(Q4+CIV)-
, , , , (2). After that, the control signal (D
) becomes high level, switch 3 is turned on, and capacitor C1 is discharged and reset.

Next, referring to FIG. 3, when the bit sign of the input signal is <"o" as shown in FIG. As it is, the capacitor C1 is not charged. Next, the control signal (C
) becomes high for a predetermined period of time, turning on switch 2 and redistributing the charge. The charge on capacitor C2 at this time is C2=(C,,/(C4+C2))・Q'2...
......(3). After that, the control signal (D) becomes high level and the switch 3 is turned on.
Capacitor C1 is discharged and reset.

Now, the input digital signal (A) is a crab bit signal (k
is a natural number), each control signal C is output from the control circuit 5 according to the procedure explained using FIG.
Charge Q accumulated in capacitor C2 at the time when B) to (D) are generated and the control operation in the final bit is completed.
2 is held in the sample bold circuit 4. This hold output becomes an analog signal corresponding to the digital input signal.

Using the above equations (2) and (3), the charge Q2 due to the bit digital signal finally obtained is as follows: 0 C2= , Σ Ql ''Z4 (C2/(c,
)) k-"1-(4)$=1 Here, Zi is 1 if the i-th bit is "1"',"
0", the value is 0. Equation (4) means that the electric charge charged in the capacitor c2 by the th pin is C2/( c, +02) times in a geometric series.

Now, since Ql is a constant determined by C1 and V,
Under the ideal state of Qo and C1-C2, (4
) formula is C2=QO, x Z< 6 (1/2)kt" ・, -
・---(s)$-1, and an analog signal is obtained from the output of capacitor C2.

In the above, the ideal case is C4-C2, but in reality there is an error in the capacitance values C1 and C2, so C, -(]-β)corc2-<1+β)co
Let's consider this. Note that okuβ<1. In equation (4), substituting the above C1 and C2 results in the following. Comparing the ideal types of equations (5) and (6), the constant difference of (1-β2) is unrelated to linearity in absolute value, and if this is ignored, ( 1+β) is 2. may or may not exist as defined by
Furthermore, the magnitude may differ depending on the (k-j) power defined by the i-th bit, causing a deviation from the ideal type, resulting in distortion and noise.

Now, considering the standardized deviation E, it can be expressed as
The deviation ΔEi when the i-th bit operates up to the final bit is ΔF,i − (1/2)k-”・(Aβ+Bβ2+・
・・・ ) ・・・Song (8). Here, if β(l), the terms greater than β2 can be ignored, so k-t+1 ΔEi = (1/2) ・Aβ... Song... (9
). The values obtained by equation (9) are shown in Table IK.

-' 7 In Table 1, the maximum distortion is when Z< is all "1#", and we will consider β under the condition that this does not exceed the minimum unit.The minimum unit for each bit number of k = 48 and 16 is , (1/2)' , (1/2)8 and (1/2)
2) ”, the maximum distortion for each part is 0688β.

Assuming that 0965β and ]・β do not exceed, respectively, the tolerance of β is 0.0909, 0.004 and O,0, respectively.
OOO]'5 is calculated.

Since the difference between capacitors C1 and C2 is 2β, this difference is allowed up to 18% for 4 bits and up to 08% for 8 pins. However, with 16 bits, only 0.003 inch is allowed, so even if a capacitor could be manufactured with an error of 01 inch, it would only be possible to realize a D/A converter of about 10 pins.

FIG. 4(A) is a diagram showing an example of analog output distortion caused by a difference in the capacitance values of capacitors CI and C2, where a curve 20 shown by a solid line is the true analog value, and a curve 21 shown by a dotted line. is the distorted D/A converter f7') analog output. Note that To indicates the sampling period. In this way, the analog output level corresponding to each sampling value shifts in only one direction (positive direction in the figure) with respect to a true analog novel, and the width of the shift differs for each sampling value set and may not be constant. This deviation results in output distortion.

FIG. 4(B) shows the shift in analog output level for each K sampling value, that is, the error component.

In order to correct this error component, capacitors C1 and C2 are connected for each digital signal corresponding to each sampling value.
A conceivable method is to perform the same operation as described above by switching the roles of the two, perform two analog conversion operations for each same digital signal, and add the two analog outputs. In this case, in the second operation, FIG. 5(A),
As shown in (B), there is a deviation only in the negative direction from the true analog value, and the deviation width is the same as that in the]th operation shown in Figure 4, so the analog output obtained by both operations is By adding the error components, the error components cancel each other out and an accurate analog signal is obtained.

However, this method requires two control operations for the same digital signal, which makes the control complicated and increases the conversion time.

An object of the present invention is to provide a highly accurate D/A converter that reduces output distortion due to the difference in capacitance of two capacitors without increasing conversion time.

The D/A converter of the present invention includes first and second converters whose one ends are commonly connected to a reference potential point, and a control means for controlling charging and discharging of these first and second capacitors according to a digital signal. and output means for deriving an analog signal in accordance with charges charged in the first and second capacitors, the control means comprising a first bit group which is a dog of the weight of the digital signal and a smaller one. For each focus in the first focus group among the remaining bit groups, the charge to the first capacitor is turned on and off according to the bit contents of and this charge is distributed to the second capacitor. The discharge is controlled, and then a zero focus is added above the most significant focus of the remaining bit group, and the same control operation as that of the first focus group is performed for each bit of the second focus group to which this zero bit has been added. None, again for each bit of the second bit group, charging to the second capacitor is turned on and off according to the focus content, and this charged charge is distributed to the first capacitor, and after that, the discharge of the second capacitor is controlled. The output means samples and holds the output of the second capacitor obtained by the operation of all bits of the first bit group by the control means and the subsequent operation of all bits of the second bit group, and The present invention is characterized in that the output of the first capacitor obtained by the operation of all bits of the second bit group is sampled and held, and these two held outputs are added to form an analog signal.

The present invention will be explained below using the drawings.

FIG. 6 is a circuit block diagram of an embodiment of the present invention.
Parts equivalent to those in the figures are designated by the same reference numerals. In this example, in addition to the circuit configuration shown in FIG. 1, charge/discharge switches 6 and 7 for the second capacitor 4c and a second hold circuit 8 that samples and holds the output corresponding to the charge of the first capacitor C1 are added. , the hold output of the first hold circuit 40 and the hold output of the second hold circuit 8 are added by an adder 9 to form an analog output.

Also in the control circuit 10 in this example, control signals (Bl to (D) and (B
').

(D) is generated respectively, and the signal (B'
) and (D'), the switches 6 and 7 are controlled to be on/off, respectively. Further, sample paths for the hold circuits 4 and 8 are also generated from the control circuit 10.

Here, of the k-bit digital input signal, it is the bit group with small weighting that causes a relatively larger error due to the difference in capacitance of capacitors C1 and C2, rather than the focused group with higher weighting. It is. So, for example, in the case of = ] 6, the first bit group of the first half of the weighting is set to the 11th bit, and the remaining bit group of the second half of the weighting, which is J\, is set to the 12th and subsequent bits. The focus group operates as before, and for the remaining bit group, the functions of capacitors C1 and 02 are reversed and are operated twice, and the charges in the capacitors obtained by these calculation operations are added together to create an analog signal. It is used as a signal.

In this case, the remaining bits in the second half are operated twice, so if they are simply added, the absolute value will be doubled. Can not. 2 for the remaining bits in the second half
It is sufficient to shift the calculation results by 1/2, but this 1
An error will occur again in the calculation process of /2.

Therefore, in the present invention, when performing an arithmetic operation on the remaining bits, a zero ("0") is placed further above the most significant bit of the remaining bits.
) bits are added, and each remaining bit is shifted down by 1/2, and a total of 6 bits, including the 12th to 16th bits and the additional bits, are made into a second bit group, and the second bit group is processed twice. This is to perform arithmetic operations.

In this way, the absolute value obtained by each one calculation operation of the second focus group is 1/1/1 of the absolute value that should be obtained by each one calculation operation of the remaining bit group without adding additional focus.
2, and no error occurs.

The above operation will be explained below using FIGS. 7 to 10.

First, the first bit group (1st bit to 11th bit) in the first half of the 16-bin digital input signal (A) and the remaining bit group (1st bit to 11th bit) in the latter half are respectively The remaining bit group is divided into two groups, and the most significant bit of the remaining bit group is added with a ``0''0'' bit to form a second bit group. The first bit group and the second bit group are treated as one digital signal, and control signals (B) to (D) as shown in FIGS. 7 and 8 are generated sequentially according to the bit contents for each focus. and switches ]~3 operate accordingly. This is the same operation mode as in the conventional example, and is the same as the timing waveforms in FIGS. 2 and 3. All bits (16
At the time when the above operation is completed (bint + added bit), the charge charged in the capacitor C2 is sampled and held by the hold circuit 4.

Although not particularly shown, the control circuit 10 includes the second
A memory is provided to store the bit contents of the bit group, and when the above operation is completed, the signal of the second bit group is read out from this memory, and this signal is read out for each bit only for the second bit group. Control signals as shown in FIG. 9 and FIG. 1O are generated depending on the bit contents.

Figure 9 shows the case where each bit is like (A) (“■”),
Since the control signal (B') is at a high level, the switch 6 is on, and the capacitor C2 is charged.

Next, the control signal (C) becomes high level, the switch 2 is turned on, and charge distribution is performed. After that, the control signal (
The signal D becomes high level, the switch 7 is turned on, and the capacitor C2 is discharged.

FIG. 1O shows the case where each bit is <"o" as shown in (A), and the control signal (B') remains at a low level and the capacitor C2 is not charged. Next, the control signal (C)
becomes a high level and charge distribution h''- is performed, and then the control signal (D') becomes a high level and the capacitor C2 is discharged.

The charge charged in the capacitor c at the time when the above operation is performed for all bits of the second bit group is sampled and held by the hold circuit 8. This hold signal and the hold signal of the first hold circuit 4 are added to form an analog signal output.

By doing this, the errors cancel each other out and disappear due to the double arithmetic operations on the lower bit groups, which are relatively similar to each other.
The error is significantly smaller than that of rotating motion. Further, since there is no need to perform double arithmetic operations for all bits, the D/A conversion time does not increase significantly.

The finally obtained maximum error E7MZ for the above example, that is, the case of 16 bins, is expressed by the following equation with reference to equation (8).

Emax=, Σ (β term and β2 term due to single operation) %==] 10 Σ (β2 term due to double operation)・・・・・・(1o
)-12 The reason why there is no β term in the second term is because they cancel each other out due to the double action.

Here, in Table 2, the terms β and β2 of equation (10) are calculated and shown.

Table 2 Based on this Table 2, when we calculate the value of the formula (lO), Enmw
= (0,187β+0.5β2) + 0.657β
2=O, 187β+1.157β2, which is obtained by conventional one-time operation -X-1・
It can be seen that the β term of β11 and β2 is improved by approximately 20%. The term β2 can be ignored if β(1).

According to the present invention, a highly accurate D/A converter can be obtained without significantly increasing the conversion time.

Note that the value of k and the number of focuses of the first bit group and the remaining bit group are not limited to these.

In particular, the number of bits may be determined based on the relationship between the difference β between the two capacitors and the desired accuracy, the number of operations that can be performed within one sampling time, and the operation speed of the converter. Further, the control circuit can be easily realized by using a program using a converter such as a microprocessor.

[Brief explanation of drawings]

Figure 1 is a circuit block diagram of a conventional D/A converter, Figures 2 and 3 are timing charts explaining the operation of the blocks in Figure 1, and Figures 4 and 5 are circuit operations of Figure 1. FIG. 6 is a circuit block diagram of an embodiment of the present invention, and FIGS. 7 to 10 are timing charts explaining the operation of the circuit block in FIG. 6. be. Description of symbols of main parts C1, C2...Capacitors 1 to 3, 6.7...Switches 4.8...Hold circuit 9...Adder 10
...Control circuit applicant Pioneer Co., Ltd. agent Patent attorney Motohiko Satoshi (1 other person) He he he he +',')++'nu's Q Q "Cω θ ○ ++J+,,ν + ○ to , to 39 shi 0 nu (Q

Claims (1)

[Claims] first and second capacitors each having one end commonly connected to a reference potential point; a control means for controlling charging and discharging of the first and second capacitors according to a digital signal; and charging of the first and second capacitors. and an output means for deriving an analog signal according to the electric charge, the control means being configured to select one of a first bit group, which is a weight dog, and a smaller residual bit group, of the digital signal. For each bit of the [first] bit group, charging of the first capacitor is turned on and off according to the focus content, and the charged charge is distributed to the second capacitor, and after that, discharging of the first capacitor is controlled. Then, a zero bit is added to the most significant bit of the remaining bit group, and the same operation control as that of the first bit group is performed for each bit of the second bit group to which the zero bit is added. , again for each bit of the second bit group, charging to the second capacitor is turned on and off according to the contents of this bit, and this charged charge is distributed to the first capacitor.
The output means is configured to control the discharge of the capacitor, and the output means outputs the output of the second capacitor obtained by the operation of all bits of the first bit group and the subsequent operation of all bits of the second bit group by the control means. Sample and hold the output, sample and hold the output of the first capacitor obtained by the second operation of all bits of the second bit group by the control means, and add these two hold outputs to obtain an analog signal. A digital-to-analog converter.