JPS6030218A - Multi-channel digital recording and playback equipment - Google Patents

Abstract

PURPOSE:To speed up circuit operation and simplify a circuit by using a generating circuit for a reference voltage which varies abruptly at the beginning and then varies slowly in a polygonal shape in common to respective channels. CONSTITUTION:An AD converter for a multichannel digital recording and reproducing device is provided. Then, two inputs L1 and R1 are held by sample holding circuits 20A and 20B respectively, compared with a ramp voltage by comparators 24A and 24B, and converted into time width values intermediately; and counters 25A and 25B count clocks from clock generators 26A and 26B, thereby outputting a digital signal 23. Then the ramp voltage is used in common to respective channels, and stepped linearly and abruptly down to a voltage VS from an initial state VE and then slowly down to a voltage VT in the polygonal shape.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a multi-channel digital recording/reproducing device, and particularly to an AD-DA converter thereof.

[Background of the invention]

Recently, digital technology has been introduced into multi-channel audio devices and the like. Furthermore, multi-channeling is also an essential requirement for an X-ray CT apparatus that processes information digitally.

Figure 1 shows A of the multi-channel digital recording and reproducing device.
A block diagram of the D-DA converter is shown.

As shown in FIG. 1, in the multi-channel digital recording/reproducing apparatus, input signals J, 2 of 2 or 4 channels are sampled and held by sample and hold groups 7 and 8, and AD converters 9 and 10 are used. At the same time, the signal is PCM-modulated into a digital signal, and the multiplexer 11. The signal is recorded and processed as a digital signal 3 via a buffer memory 12. Thereafter, the digital signal 4 passes through the buffer memory 13 and 14 multiplexers to the DA converter 15.
a multi-channel digital recording and reproducing device in which the output signals 5 and 6 of the sample and hold groups 17 and 18 are simultaneously converted into analog quantities by 16 and reproduced as analog signals;
In particular, AD/1) for digital audio recording and playback equipment.
As an A converter, resolution is 16 bits or more, conversion time is 1
A high performance device with a performance of 0 μ5 eti or more is required.

Integral method AI) as a high-resolution aL1 high-performance converter
A DA converter is known, but its performance is limited to a resolution of about 16 bits and a conversion time of about [m(8)], and it cannot be used if even higher speeds and higher resolutions are safe. This was the current situation.

In addition, the cascade integration method is an improved version of the above integration method (low distortion 16-bit l0A-D, D-A for digital audio).
Converter: Published in Nikkei Electronics 1982, No. 1.18) has the above performance (16 bits per minute, conversion time ('J
JIOμSα, ), but it has the disadvantage that it cannot be multi-channeled.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to overcome the drawbacks of the prior art as described above and to provide a high-speed, high-performance multi-channel digital recording and reproducing system.

[Outline of invention cost]

In order to achieve the above objective, the present invention employs a first power integral type AD-DA conversion method as the AD-DA converter in a multi-channel digital recording/reproducing device having an Ai)/DA converter for each channel. , the reference voltage IIE changes rapidly at first and gradually changes in a line-shaped manner.
By providing a (ramp function) generation circuit so that each of the channels can be used together, the circuit can be made faster and simpler, and the gain and offset fluctuations that differ for each channel are made the same for all channels. Have you tried to improve the deterioration of audio signals, etc.? Features.

[Example of invention]

Hereinafter, one embodiment of the present invention will be described based on all the drawings. Figure 2 shows the entire A1) converter for multi-channel digital recording equipment according to an embodiment of the present invention, (a) is a circuit block diagram, and (b) shows signal waveforms of each part. It is.

In Fig. 2, 19A and 19B are integrators for generating the ramp function 21, and 20A and 20I3 are channel L.
l-R1 input signal sample hold circuit, 24
A, 24B, 24C, 24D are comparators, 25A, 25B
is a counter, 26A and 26B are clock generators, 27A
-27B is a control circuit. Further, -VE and -VS are constant voltage sources, -1o (-1+) are constant current sources, Sl-S4 is a switch, R is a resistor, and C is an integrating capacitor.

The entire operation of the circuit shown in FIG. 2(a) will be explained below.The comparison reference voltage level between the ramp function 21 and the input signal? Let the input signal levels of the LL and R1 channels sampled and held in the VT and sampling circuits 2OA and 20B be VL and VR, respectively.

When the ramp function 21 is generated as follows, the switches S2, δ3, and 84 are opened, and the switches S1 and 84 are closed. Press -/14)・■
Photoelectricity is applied up to s. Immediately, when δ1 is opened and closed to 82, the ramp function Ll is obtained.

is discharged to the level of vS, after which switch S2i
When the opening 83 is closed, the lamp I uniformity L I 6 will be discharged to the reference level VT. Here, the current value 1o of the constant current source Io-io, the ratio of 1o is 1°=256 i.

Then, the slope between VE and VS is 256 times the slope between VS and VT. When performing AD conversion with 16-bit precision, the first broken line (between VE and VS) has a frequency of 2561. It is counted with the weight of SB, and on the second odd line (between VS and VT) it is counted with the weight of ILSB (7). At this time, the clock frequencies of the clock generators 26A and 26B are the same for the first broken line and the second broken line.

VS-VT is set to a voltage value of 1/256 of VE-VT of the ramp function. Sample hold circuit 20A/2
Input signal Ll-I( sampled and held by 0B)
, 1 are compared with the ramp function by comparators 24A and 24B, and when each level VL-VR is higher than the ramp function, "'1" k is output. Clock generator 26A・2
6.3 immediately generates a clock when the outputs of the comparators 24A and 24B reach 1", and this clock number counters 25A and 25B count.
25B is cleared by the falling signal of the comparator 24D, the clock generators 26A and 26B perform four counting operations at the "1" level, and the level of the ramp function Lio becomes lower than VT, and the output of the comparator 24D becomes When the level reaches 1'', the counting operation stops.

In the initial state, ν;, as shown in FIG. 2 (1), the level VE(7) of the ramp function 21 is V'l'-VL・
VI (very high. Therefore, comparators 24A, 24B, 2
The output of 4D is 0'', and the clock generator 26A.2
6 i( is in the 01'F state.

In this state, a ramp function sound is generated, and when the ramp function Ljo falls below the input signal level vL, the comparator 24
The output of A becomes 1''°, a cyclic clock is generated by the clock generator 26A, and the counter 25A starts counting.After that, the lamp opening number LIO becomes the same as the voltage VSk of the switching υ of the broken line and the lower clock 26A. control circuit 27A
・27 F3 switches the ramp function to Lio, which is the same level as Llo, and at the same time, the broken line switching signal 22 is turned on.
Weight counter 25A according to the difference in slope of the two broken lines
For example, the above ■o-2561
If ov'M, the counter 25Ak is shifted 8 hits upward. Generally, when using a binary counter, 1. o
When switching between two broken lines whose slopes are changed so that there is a relationship of -2X'o, the counter is shifted by n bits to the upper part.

Next, when the ramp function Ljo enters the input f8 and becomes lower than the bell VRr, the ratio +17 (the outputs i"i" and xb of the device 24I3, and during that period a clock is generated from the clock generator 26■3, and the counter 25B counts ?υ[ The first step is to start, and by this time,
2 on the counter is n (= 8) due to number 22 on the broken line switch f
Only the bits have been shifted upward, but the counter I has changed again.
Since the content of 2 is N O++, the content has not changed.

Furthermore, when the ramp function] J'O falls below the reference voltage VTk, the output of the comparator 241J becomes lI+ (c) The two counters 25A and 25B complete counting, and the contents are memorized. That is, each counter 25A・The count number corresponding to the difference between each input No. 18 level Vl, -Vl (and the reference voltage VT) remains in 25B.

This digital callan l-1,? ll-digital signal Wd
J 23 ', C, the audio signal, etc. is read out and transferred to the buffer memory 12 shown in 1.
The CM recording operation ends.

FIG. 3 shows a multi-channel system according to an embodiment of the present invention.
1) A converter display for digital recording and reproducing equipment, (a)
O-circuit block diagram, (b) is the signal waveform of each part? This is what is shown.

In FIG. 3(a), 190 is an integrator, 20C.
D is a sample hold circuit, 24E is a comparator, 25C.
25D and 25E are color circuits, and 28A and 28B are latch circuits. Also, IO'IO is a constant current, S5 and S6 are switches, and C is a (1(min) capacitor.

The entire operation of the circuit shown in FIG. 3(a) will be explained below.Reference m pressure t/herk V T , full scale level kVl:
The switching of the two broken lines of the ramp function is assumed to be vs.

The relationship between VT, VE, and VS is the same as in the case of the above AD converter, when lo -25610, I between VE and VS is
The slope of o is 256 times the slope of 1° between VS and v'r. Moreover, the voltage fiM of VE-VS is VS-
VT(7) electric EE value (relationship: IDI/256).

In the integrator 19C, switch S6i opens switch 5
When 5=i is closed, charging is performed with a slope of io.

On the other hand, the digital manual DL-DI also has a latch circuit 28A.
28B and further moved to counters 25C and 25D. Here, the 16-bit DA
Considering the conversion, the contents of the upper 8 bits of counters 25C and 25D indicate the weight of Io, and the contents of the lower 8 bits are i.
The weight of o is shown. Integrator 19C charged with io
When the output of the counter 25E exceeds the reference value V'l''2, the contents of the lower bit of the counter 25E are counted down, and the integrator 19C is charged by the full scale contents of the counter 25H. When the contents of the carry CRL are issued, the switch S5 opens and the switch S6' closes.Then, bw of the upper bits of the counter 25E is counted down, and the integrator 19C(]l- is further charged by the full scale content of the counter 251. .The upper bits of counter 25E are carry CJ.
+, U When the signal is issued, the stopper S5.86 is opened and the integral operation is completed. And sample bold circuit 20
C・20 To sample and hold the integral t according to the contents of the DVC counters 25C and 25D, use the analog signal L2.
・T(, 2k can be taken out @.

In the initial state, as shown in FIG. 3(b), digital human power L7, L-D1. i is the latch circuit 28
Latch with A・281J, counter 25C・25J
When the output of the integrator 19C is set to J and exceeds the reference level, the counter 25E and the counter 25C and 25
At the end of the countdown of D, the signal CAL+ ・CAL2 is counted down with a weight of ILSH in the interval from 2JVT to vS, and then counted down with a weight of 256LSH in the interval from VVS to VE.
The output r of the integrator 19c according to the value of the lower bit of the counter 25C/251) is the sample hold circuit 20C.
・201) is sampled and held, and further the signal CA,
The output of the integrator 19C corresponding to the second bit j'4 of the counters 25C and 25D is sampled and held in the sample and hold circuits 20C and 20D by lJI-CAIJ2 and added. At this time, the frequency of the clock CLK is the same as when counting down the lower bits and when counting down the -ay bits. 'F(ff
The output of integrator 19C becomes VSK by bit countdown.
cycle occurs when the lower bit is at full scale,
The output of R19C reaches VE-VS by 47 minutes in the countdown of the upper bit when -1f kebit is at full scale. In the figure, VL2 is the counter 2.
Output of integrator 19C at the end of 5C countdown'
The FJL voltage, VB2, is the output voltage of the integrator 19C at the end of the countdown of the counter 25D.

In this way, sample bold circuits 20C and 20D
The signal sampled and held is the analog output signal L2
- Extracted as R2.

In addition, in the above-mentioned actual example, explanation was given using two broken lines, but it is also possible to expand to three or more broken lines.

In this way, when each channel has an AD-DA conversion function, there is no need for high-speed multiplexers, sample-hold circuits, etc. that are required when processing multiple channels with a single AD-DA converter. Moreover, noise increase due to the broadband characteristics required for high speed can be avoided.

〔Effect of the invention〕

As explained above, according to the present invention, by using one ramp function in common for all channels, even if the offset and kein of the ramp function fluctuate, one of these functions acts commonly on all channels. Therefore, it can be easily corrected by digital processing, and by changing the shape of the ramp function to a broken line instead of a straight line, it can be used to improve business and refinement.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an AIJ-DAA conversion section of a conventional multi-channel digital recording/playback device, and FIG. 2 illustrates an AD converter of a multi-channel digital recording/playback device according to an embodiment of the present invention. FIG. 3 shows the multi-channel digital recording/reproducing device OD of the present invention.
It is a diagram for explaining the entire A converter.

Claims (1)

[Claims] 1. In a multi-channel digital recording and reproducing device having an AD-DA converter for each channel, the above A
The D-DA converter uses a single integral type AD-DA conversion method, and the circuit generates a reference voltage (ramp function) that changes rapidly at first and then slowly changes in a linear fashion. Did you provide the channels so that they can be used together? A multi-channel digital recording and playback device.