JPS6030635U - flip flop circuit - Google Patents

flip flop circuit

Info

Publication number
JPS6030635U
JPS6030635U JP12183683U JP12183683U JPS6030635U JP S6030635 U JPS6030635 U JP S6030635U JP 12183683 U JP12183683 U JP 12183683U JP 12183683 U JP12183683 U JP 12183683U JP S6030635 U JPS6030635 U JP S6030635U
Authority
JP
Japan
Prior art keywords
transistor
base
emitter
whose
output terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12183683U
Other languages
Japanese (ja)
Inventor
東 洋二
Original Assignee
日本電気アイシ−マイコンシステム株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日本電気アイシ−マイコンシステム株式会社 filed Critical 日本電気アイシ−マイコンシステム株式会社
Priority to JP12183683U priority Critical patent/JPS6030635U/en
Publication of JPS6030635U publication Critical patent/JPS6030635U/en
Pending legal-status Critical Current

Links

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来の電流切換型リセット付のフリップ・フロ
ップ回路の一例の回路図、第2図は本考案の一実施例の
回路図である。 1〜13・・・・・・トランジスタ、■1〜I、・・・
・・・定電流源、Inl・・・・・・データ信号端子、
In2・・・・・・クロック信号端子、In3・・・・
・・リセット信号端子、R工9 R2・・・・・・抵抗
FIG. 1 is a circuit diagram of an example of a conventional flip-flop circuit with current switching type reset, and FIG. 2 is a circuit diagram of an embodiment of the present invention. 1 to 13...transistor, ■1 to I,...
...constant current source, Inl...data signal terminal,
In2...Clock signal terminal, In3...
...Reset signal terminal, R engineering 9 R2...Resistance.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] ベースがデータ信号端子に接続しコレクタが否定出力端
子に接続される第1のトランジスタと該第1のトランジ
スタのエミッタにエミッタが接続されコレクタが背定出
力端子に接続される第2のトランジスタとで構成される
データ書込み回路と、コレクタが前記否定出力端子に接
続しベースが前記背定出力端子に接続する第3のトラン
ジスタとベースが前記第3のトランジスタのコレクタと
前記否定出力端子とに接続しコレクタが前記第3のトラ
ンジスタのベースと前記背定出力端子とに接続されエミ
ッタが前記第3のトランジスタのエミッタに接続される
第4のトランジスタとで構成されるデータ保持用回路と
、前記第1及び第2のトランジスタのエミッタの共通接
続点にコレクタが接続する第5のトランジスタと、前記
第3及び第4のトランジスタのエミッタの共通接続点に
コレクタが接続しエミッタが前記第5のトランジスタの
エミッタに接続される第6のトランジスタ゛   と、
エミッタが前記第5のトランジスタのベースに接続しコ
レクタが接地されベースが前記第2のトランジスタのベ
ースとリセット信号端子とに接続される第7のトランジ
スタと、エミッタが前記第6のトランジスタのベースに
接続されコレクタが接地されベースがクロック信号端子
に接続される第8のトランジスタと、前記否定出力端子
と接地との間に接続される第1の抵抗と、前記肯定出力
端子と接地との間に接続される第2の抵抗と、前記第5
及び第6のトランジスタのエミッタの共通接続点に接続
される第1の定電流源と、前記第5のトランジスタのベ
ースと前記第7のトランジスタのエミッタとの接続点に
接続される第2の定電流源と、前記第6のトランジスタ
のベースと前記第8のトランジスタのエミッタとの接続
点に接続される第3の定電流源とを含むことを特徴とす
るフリップフロップ回路。
a first transistor whose base is connected to the data signal terminal and whose collector is connected to the negative output terminal; and a second transistor whose emitter is connected to the emitter of the first transistor and whose collector is connected to the negative output terminal. a third transistor having a collector connected to the negative output terminal and a base connected to the negative output terminal; and a third transistor having a base connected to the collector of the third transistor and the negative output terminal. a fourth transistor, the collector of which is connected to the base of the third transistor and the constant output terminal, and the emitter of which is connected to the emitter of the third transistor; and a fifth transistor whose collector is connected to a common connection point of the emitters of the second transistor, and whose collector is connected to a common connection point of the emitters of the third and fourth transistors and whose emitter is connected to the emitter of the fifth transistor. a sixth transistor connected to;
a seventh transistor whose emitter is connected to the base of the fifth transistor, whose collector is grounded and whose base is connected to the base of the second transistor and the reset signal terminal, and whose emitter is connected to the base of the sixth transistor; a first resistor connected between the negative output terminal and ground; and an eighth transistor connected between the positive output terminal and ground. a second resistor connected to the fifth resistor;
a first constant current source connected to a common connection point between the emitters of the sixth transistor; and a second constant current source connected to a connection point between the base of the fifth transistor and the emitter of the seventh transistor. A flip-flop circuit comprising: a current source; and a third constant current source connected to a connection point between the base of the sixth transistor and the emitter of the eighth transistor.
JP12183683U 1983-08-05 1983-08-05 flip flop circuit Pending JPS6030635U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12183683U JPS6030635U (en) 1983-08-05 1983-08-05 flip flop circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12183683U JPS6030635U (en) 1983-08-05 1983-08-05 flip flop circuit

Publications (1)

Publication Number Publication Date
JPS6030635U true JPS6030635U (en) 1985-03-01

Family

ID=30278706

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12183683U Pending JPS6030635U (en) 1983-08-05 1983-08-05 flip flop circuit

Country Status (1)

Country Link
JP (1) JPS6030635U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62123297A (en) * 1985-10-23 1987-06-04 Hitachi Ltd Heat exchanger performance improvement device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62123297A (en) * 1985-10-23 1987-06-04 Hitachi Ltd Heat exchanger performance improvement device

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