JPS60309A - Method and apparatus for testing pattern of print - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method and apparatus for inspecting patterns on printed matter.

As shown in FIG. 1, the conventional printed matter pattern inspection apparatus extracts image information by scanning a printed matter 1 in the width direction with a line sensor camera 2, and on the other hand, outputs from a rotary encoder 4 attached to a cylinder 3 of a conveyance system are used to scan the printed matter 1 in the width direction. By synchronizing the scanning of 2, the sample pattern 5 (FIG. 2) is divided into a large number of small pixels in a matrix.

The density of each of these pixels is sequentially compared with the corresponding small pixels of the sample pattern 6 (FIG. 2), which has been similarly divided and recorded in the memory, to detect the presence or absence of a defect.

In this type of pattern inspection, if there is a positional shift in the width direction of the conveyance system as shown in Figure 3, the gradation obtained from the specimen will change for the 3 pixels marked with O out of the 7 gradations obtained from the sample. When compared with the corresponding three pixels of No. 8, the sample pattern is erroneously determined to have a defect even though there is no defect.

One possible way to prevent this is to set a large tolerance value for the gradation difference between the sample and the specimen.

However, this results in a decrease in defect detection accuracy and is not necessarily a good countermeasure.

A method that does not have such problems is to correct the positional deviation of the sample pattern with respect to the sample pattern.
Various methods have been devised.

The first method, as shown in Japanese Patent Application No. 56-146355 filed by the applicant, is to detect the position of the pattern of the printed matter in the width direction, and this position change causes the data of the sample pattern to be written into the sample pixel data memory. If the result of comparing the time and the time of reading the sample picture data is that the data differs by more than a predetermined value, the sample picture data at that time is written into the sample pixel data memory.

However, this method requires a device for detecting positional changes in the width direction of the printed matter and correcting positional deviations according to the positional change information, resulting in problems of complicated hardware and rising costs.

Part 2 is shown in Special Publication No. 55-45948.

This method compares a sample pixel with several pixels in the vicinity of the corresponding sample pixel.

However, this method has a problem in that inspection accuracy inevitably deteriorates.

Part 3 is Japanese Patent Application No. 57-151, 11 filed by the applicant.
8, the width direction picture gradation data of the sample (hereinafter referred to as sample row data) is compared with the corresponding width direction picture gradation data of the sample (hereinafter referred to as sample row data), and detection is performed for each sample. This method refers to a plurality of sample properties shifted by the positional deviation allowed by the sample property, and performs a °C pattern inspection using the sample property and the sample property whose phase is closest to the sample property.

However, with this method, depending on the positioning accuracy of the sample transport system, the number of specimens required is very large (and at the same time, the transport system is required to have high precision, so it is difficult to simplify and reduce costs). It has been desired to develop a method for correcting positional deviations that is more efficient.

〔overview〕

The present invention has been made in consideration of the above-mentioned points, and when comparing the pattern data taken out from a sample print with the pattern data taken out in advance from the sample print and stored in a memory to determine the quality of the pattern, A plurality of pieces of data are formed by shifting one of the sample line data detected line by line from the sample and the sample line data stored in the memory relative to the other in units of one pixel. The sample row data and the sample row data are compared using a plurality of data, and the positional deviation between the two data is determined from the positional relationship between the two data when the level difference becomes the minimum value, and the amount of this positional deviation is calculated. An object of the present invention is to provide a method and apparatus for inspecting a pattern of a printed matter, which corrects the address of one of the above-mentioned data based on the following.

〔Example〕

Embodiments of the present invention will be described below with reference to FIGS. 4 to 21.

FIGS. 4(a), (b), and (C) show sample row data and sample row data, and FIG. 4(a) shows the relationship between sample row data and sample row data handled in the method of the present invention. The basic relationship is shown. Figure (b) shows the relationship between the amount of positional deviation and the number of defects for both data, and Figure (c) is the sample row data in a special part characterized by the edge of the printed matter. This shows the relationship between the data and the sample row data.

First, according to FIG. 3A, a plurality of sample row data 10 to 16 are referred to for one sample row data 9. These sample row data 10 to 16 are obtained by shifting the basic sample row data 13 one pixel at a time to the left and right by a positional shift n that is predicted based on the accuracy of the transport system.

Then, the concentration of the sample row data 9 can be compared with the sample row data 12 which is closest in phase to the sample row data 9 among the sample row data 10 to 16, and thereby defects are detected.

As a result, even if the sample row data 9 is misaligned in the width direction of the printed material, the data can be compared with each other in terms of content (defects can be detected). The method for selecting the one whose phase is closest to the data is as follows.

As shown in FIG. 4(b), defect detection is performed for each of the plurality of sample row data for one scanning period of the camera 45;
The number of defects in the sample row data that is closest in phase to the sample row data is minimized compared to other samples. That is, for each scan, the sample row data with the minimum number of defects is the sample row data at that time,
This means that the phase is closest. However, this illustrated example relates to a relatively light image, and an image with a strong degree of shading has a characteristic curve with a larger slope.

Next, according to FIG. 3C, the sample row data 18 having the closest phase to the sample row data 17 is compared, and a large tone difference tolerance is set. This makes it possible to carry out defect inspection suitable for cases where the gradation difference is extremely large, such as at the edge of a picture. That is, since the sample row data 18 is closest in phase to the sample row data 17, the phase difference between the two is A pixel width. Therefore, the tone difference between the sample and the sample at the pixel corresponding to the edge when a positional shift corresponding to the difference pixel width occurs may be used as the tolerance value for that pixel.

The permissible value setting for each pixel can be carried out using the method of Akihiro (see Japanese Patent Application No. 56-179599), or pixels corresponding to edges may be masked to be excluded from the determination.

FIG. 5 shows the configuration of an apparatus for carrying out the method of the present invention, which is constructed based on the idea of FIG. 4.

In this device, a conveying cylinder 3 for conveying printed matter 1
The amount of rotation is detected by the rotary encoder 4 and input to the synchronization circuit 21. A scanning position detection signal from the camera 2 is similarly input to the synchronization circuit 21, and an arbitrary position on the printed matter I is detected. This synchronous circuit 2
Based on the output of camera 1, A/D converter n converts the analog quantity input from camera 2 into a digital quantity. Here, the circuit that assigns addresses to the printed matter 1 based on the information from the synchronization circuit 21 is the address correction circuit. The important function of this circuit is to correct the next row to the optimum address by feeding back the output result of the determination circuit regarding the sample row pattern that is closest in phase to the sample row pattern.

Then, after storing the digital quantity for each detected pixel in the sample pixel data memory 5, from the next screen, the sample row data is processed in the judgment circuit in real time with a plurality of shift row data generated from the sample pixel data memory 5. be compared. On the other hand, the determination level is determined in real time from the data in the determination level data memory 2B set in advance by the determination level setting circuit 27 and the data in the sample pixel data memory 5, and is output to the determination circuit B.

In addition, in the figure, from the address correction circuit to the determination circuit 23
The signal shown by the broken line given by 1C is used when correcting the sample pixel data from camera 2 to the optimum address.

In this case, the determination circuit B is required to have a shift register or the like and be able to shift the sample pixel data one pixel at a time.

FIG. 6 shows a more specific configuration of the judgment circuit B in the apparatus shown in FIG. 5, taking as an example a shift amount of ±3 pixels and 512 pixels per row, and shows sample row data SD and judgment level data MD for one pixel. Latches L1 to L for shifting by
3 and a shift circuit using latches L4 to L6Vc for shifting the sample row data TD by one pixel are respectively determined by decision elements JE, ~JE3 and JE4.
~JE7 is combined with a group of determination elements.

Each shift circuit performs a shift operation by applying the clock CLK used for scanning the camera 2 (Fig. 1) to the latch circuit. (1°For example, sample row data TDI is latch L4.L.

Shift sequentially in synchronization with camera scanning from L6 to T.
D2. TD3. It will be TD4. Similarly, ICm main line data SDI and judgment level data Ml)l are latch L1
゜L2. Sequentially shifted by L3 in synchronization with camera scanning tL MD 2 t MD3 t MD4 O, t:
HISD2+SD3+SD4@And the sample row data TT)l is the judgment Nilemen)JE□.

JE21 JE3. The data is given to JE4 and compared with sample row data and judgment level data. In other words, in JE4, the judgment is made based on sample row data TDI, sample row data SD1, and judgment level data MD1. , TDl and SD4 in JE3. Judgment is made using MD4. As a result, judgment is performed when the sample row data and judgment level data are delayed with respect to the sample row data.

On the other hand, on the other hand, when the sample row data is delayed relative to the sample row data and pixel control data, the judgment is made using the judgment elements JE, JE6. Performed by JE7.

This results in determination elements JE, ~JE.

A comparison judgment is made between the sample row data 9 and the sample row data 10 to 16 in FIG. 4(a) based on the valleys.

At this time, the output of each determination (JE1 to JE) is the number of defective cylinders detected during one scan of the camera.

The output from these seven judgment elements is the comprehensive judgment circuit T
Given to JU. The comprehensive judgment circuit TJU selects the minimum value from among the number of defective cylinders output from each element, and makes a pass/fail judgment based on whether the value exceeds a threshold value. That is, a comparison is made between the sample row data and the sample row data that is most in phase. Furthermore, by identifying the determination element that gives the lowest number of defective cylinders based on the calculation result of the comprehensive determination circuit TJU, it is possible to know how many pixels the sample row data currently being inspected deviates from the sample row data. This identification data is transferred from the output terminal ST to the address correction circuit to correct the leading address for the next one scan of the camera.

(Figure 7 is a judgment element used in the judgment circuit in Figure 6)
This article shows a more specific structure of JE. this is,
It is composed of an absolute value detection circuit DA, a comparator CP, a counter CT, and a latch LA. Then, the absolute value circuit DA of the difference calculates each sample row data TD (TD1 to TD
4) and each sample row data SD (SD, ~5D4), calculate the pair value ITD-8DI. This value and each judgment level MD (MDs) given from the judgment level setting circuit 27
~MD4) by a comparator CP, and pixels that are equal to or higher than the determination level are treated as defective signals and output to the counter CT.

The counter CT is initialized every time a scanning start signal 5ZERO, which is generated every time the camera starts one scan, is input, and can count only while a defect signal is being output. The clock CLK of the counter CT is a clock used for timing generation of the inspection apparatus according to the present invention, and one clock corresponds to one pixel in image scanning by a camera. That is, in counter CT, 1 of the camera
The number of defective pixels occurring during the scanning period is counted. The latch LA outputs the number of defective cylinders occurring during one scanning period to the comprehensive judgment circuit TJU as a signal FN (FN□ to FN7) in response to a scanning end signal 5END generated every time one scan of the camera is completed.

FIG. 8 shows a more specific configuration of the absolute value circuit of the difference in the determination element of FIG.
11AD2, an exclusive OR circuit EX, and an inverter INV, and receives TD and SD as inputs to form an output ITD-8DI. Since this circuit is well known, detailed explanation will be omitted.

FIG. 9 shows the overall judgment circuit TJU in the judgment circuit of FIG.
The configuration is shown in more detail, and is composed of six low value detection circuits MIN1 to -N6, a comparator CP, and a judgment element identification circuit JA.

Judgment elements JE□ to JE7 (Figs. 6 and 7).

The low value detection circuits MIN1 to MIN6 detect the minimum number of defective cylinders FN1 to FN7 from FIG. Comparison is made by comparator CP, and scanning lines exceeding the allowable number are treated as defective lines and a detection signal is sent to output terminal 0UTP.
Output to UT. The allowable number of defects given here is a value obtained by adding a value within an allowable range for the quality of printed matter to a value for preventing misjudgment due to noise or the like.

In addition, this comprehensive judgment circuit TJU includes a judgment element identification circuit JA in order to detect which sample row data has the closest phase (minimum number of defects) to each sample row data group shifted by ±3 pixels. It is provided. The output ST gives information on how many pixels the amount of positional deviation is when the camera is currently scanning compared to when the sample row data was taken into the inspection device.

FIG. 10 shows a more specific configuration of the low value detection circuit MIN in FIG. , A>B is obtained. One of these goes to JA as a determination element identification signal J, and the other becomes a signal for selecting a low value from inputs A and H at selector SE. The output of this circuit is 2 human power A, B
This is the signal MIN (A, B) whose low value was detected from .

Here, the comprehensive judgment circuit shown in Fig. 9 detects a low value by combining two of each of the seven inputs, compares the low value detection results with each other to detect a low value, and then performs one more stage of low value detection. The system is designed to detect the lowest value among the seven human forces.

FIG. 11 shows the judgment element identification circuit J in FIG.
This shows the operation details of A. In Figure 11,
II I It in the chart is the output J of the low value detection circuit
is a state where A) satisfies B, +1φ book 1 is a state where A<B is satisfied, and IIXI+ is a state where either of these is acceptable. 51 to J6 respectively satisfy the conditions shown in the chart, it is possible to identify which of the outputs FNI to FN7 from the seven determination elements JE is the smallest.

FIG. 12 shows the determination element identification circuit J in FIG.
This shows a more specific configuration of A, and the inverter IN■
1~INv61. This is an example of a circuit in which the logic is configured by t-7 circuits OR1 to OR6 and an encoder EN.

The applicant has already applied for the method of setting the judgment level (patent application filed in 1973).
6-179599), it has a configuration that can be used for the judgment results of the judgment circuit in real time, and furthermore, it is difficult to make erroneous judgments.

Here, three types of determination levels are employed. The first one is called 11 fixed portion 11, and is the lowest value for the shadow part (low density part) of the printed image, or
Maximum value for areas that do not require inspection (margin areas) (
255) in 8 bits. This is written in advance in the judgment level data memory.
This is called the proportional portion 11, and is a value obtained by multiplying the sample pixel data b by a certain ratio K (K(1)), and is expected to improve inspection performance.

The third one is called II edge 11, and by giving the difference between adjacent pixels in the sample pixel data memory 5 as a determination level, it is useful for preventing malfunctions in areas where the density suddenly changes. Second. The third judgment level is the sample pixel data.
Calculations are performed from memory 5 in real time.

When giving a judgment level for a certain pixel, by selecting and using the maximum value from the three types of judgment levels mentioned above,
This makes it possible to configure an inspection device that is unlikely to make false judgments. In other words, when the level difference between pixels in the sample pixel data SD is small, the first judgment level is used, and when the level difference between pixels is somewhat large due to gradation changes, the second judgment level is used. If the difference between the levels is extremely large, the third determination level is used. This kind of response prevents misjudgments.

FIG. 13 shows a specific example of the configuration of the judgment level setting circuit n shown in FIG.

One of the sample pixel data SD is a latch 1. A3゜Li2
The absolute value circuit D of the inverter INV difference is shifted using
A2. Differences between adjacent pixels can be detected at DA3.

In the high value detection circuit HLI, the larger one of the differences between the left and right adjacent pixels is sent to the B input of the high value detection circuit HL2 as a +1 step 1 judgment level. In this way, by comparing the pixel with adjacent pixels on both the left and right sides, it is possible to deal with positional deviation in the width direction on either the left or the right side using one determination level. 51 of the sample pixel data SD is multiplied by a certain coefficient K (K<1) in the proportional component setting circuit R8, and then sent to the high value detection circuit HL.
The 11 proportions are sent to the C input of 2 as 11 judgment levels.

The reason why the sample pixel data SD is output from the latch LA4 is to match the phase of the pixel with the 11 judgment level for 11 steps. For the same purpose, when quoting the 11 fixed portions of 11 judgment levels from the judgment level data CD, the phases are matched by the latches LAI and LA2, and these are input A to the high value detection circuit HL2.

The high value detection circuit HL2 selects the maximum judgment level from inputs A, B, and C, that is, the optimum judgment level obtained from the level difference between pixels in the corresponding area of the sample pixel data SD,
The determination circuit 27 uses that value as the determination level MD of that pixel.
Send to.

This series of operations is performed by the timing clock CL of the inspection equipment.
Since this is performed in synchronization with K, a determination level can be given in real time to a determination circuit that performs pixel-by-pixel comparison between sample row data and sample row data.

Here, the absolute value circuit DA2. DA3 has the same configuration as that in FIG. 8, and also includes a high value detection circuit HLI.

Since HL2 can be realized by the reverse function of the low value priority circuit MIN shown in FIG. 10, the circuit diagram is omitted.

FIG. 14 shows a specific example of the proportional portion setting circuit R8 of FIG. 13. In this embodiment, for the sake of simplicity, a specific judgment level is obtained by selecting G1 to G4 with the decoder DE without using a multiplier or the like. Further, the proportional portion setting value is 2 bits. For the input of gate G1, the most significant bit is connected to LOWK, and the lower 7 bits are connected to the upper 7 bits of the sample pixel data SD (the remaining 1 bit is not connected), so that when this gate G1 is selected, the sample pixel data SD 50% of the value is output. Similarly, the input system is connected so that by selecting 02 to G3, values of 25%, 12.5%, and 6.25% of SD are output, respectively.

When considering a conveyance system for printed matter 1, such as a printing press rewind inspection device, as shown in FIG. 15, considerable widthwise positional deviation occurs depending on the running accuracy of the conveyance system.

Furthermore, essentially in the printing process, the flow of the web supplied from the paper feed section shifts in the width direction in some cases, so the printing cylinder is often moved in the width direction during the printing stage. At this time, naturally, the sample row data will move sharply in the width direction. Therefore, for a long period of time, such as between scanning positions a and c, it is expected that a considerable amount of widthwise positional deviation will occur. On the other hand, for an extremely short period of time, such as between a and b, which corresponds to one scanning period of the camera, there is no significant widthwise positional shift (a margin of about 1 to 2 pixels is sufficient). . Therefore, countermeasures against long-term positional deviation in the width direction are more necessary, but preparing a large number of sample row data for this purpose places a very heavy load on the hardware.

Therefore, in the present invention, short-term deviations (positional deviations that occur between a and b) are dealt with using a small number of sample row data (±3 pixels in this embodiment), and long-term positional deviations (a, With respect to the positional deviation that occurs between c and c, the hardware load is significantly reduced by correcting the scan start address to the address with the smallest positional deviation before each scan of the camera.

FIG. 16 shows the timing at which address correction is performed before the camera scan.

This correction operation is performed based on the starting point and ending source of camera scanning. Based on the signal from the rotary encoder 4, the rotation direction of the cylinder 3 is divided, and the camera scanning start points are grouped together, for example, Nl and N2, and the corresponding end point is ED.
,, ED. A start signal 5ZERO is generated at each scan start point Nl and N2 of the camera, and a scan end point ED,
, ED2, an end signal 5END is generated.

From the scan end point 5END to the scan start point 5ZERO, the camera accumulates the amount of light, and the inspection device itself does not perform any calculation operation. During this period, the position shift is corrected in real time by correcting the next camera scan start address based on the address of the sample row data that is closest in phase to the ST double signal sample row data obtained from the judgment circuit. is possible.

Figure 17 explains the definition of the ST-fold signal position shift amount output from the judgment circuit. This is data obtained by shifting the sample row data G1 in order to match the data, and G2 is defined as a shift in the e direction, and G3 is defined as a shift in the ■ direction. That is, in this embodiment, by decoding the ST multiplied signal having 3 bits of information,
It can be determined to which point within ±3 pixels the currently captured sample row data is located closest to the sample row data. If you organize this, it will look like the table below.

FIG. 18 shows a specific circuit configuration example of the address correction circuit array. This circuit is composed of three types of counters C1 to C3, a latch LA5, an inverter INV, an AND circuit AND, and an OR circuit jlK)R.

Here, the 5CLK signal is a signal output from the camera,
In synchronization with this one clock, information of one pixel is taken into the inspection device. A CLK signal is generated from this signal within the inspection device to control internal timing. The 5CLK signal is a signal generated by the camera, so when no address is generated, that is, from the 5END signal to the 5CLK signal.
Although it occurs during the ZERO signal, the CLK signal
This signal is 5ZERO because it is generated within the inspection equipment.
There is no output for the period between SEND and SEND. Therefore, the number of clocks that can be used as timing signals for address correction is 5.
CLK (becomes number i.

FIG. 19 shows the generation timing of various clocks φ1 to φ7, and address correction is accurately performed between the 5END signal and the 5ZERO signal.

Each counter C1 to C3 has a preset function, and
When the oad terminal is LOW, preset data is output. C1 is the ST flaw signal preset data from the determination circuit n, and the number of misaligned pixels is counted. C
2 is an up/down counter, which uses the address at the end point of one scan before as preset data, and C1
The address obtained by counting up or down 5 CLK signals by the number of pixels counted in is output as the address closest in phase to the current sample row data to the preset data of the internal address generation counter C3. C3 generates an internal address in which the scanning start address of the camera is optimally corrected based on the preset data from C2. Here, the internal address is treated as 16 bits. This output is used as an address for writing and reading data into memory.

Next, the clocks φ1 to φ generated at the timing shown in FIG.
7.Explain each function.

The determination circuit outputs an ST flaw signal in synchronization with the 5END signal. Clock φ with time margin for this data to be determined
2, it is taken into latch LA5. The most significant bit of the output of latch LA5 is input to up/down e-counter C2 as data indicating the shift direction of sample row data.

In C2, after the up state and down state are determined, preset data (scan end address of the previous scan) is output at clock φ3. However, counting is not performed while the clock φ1 is Low (preset mode). On the other hand, the lower 2 bits output of latch LA5 are output from inverter IN.
It is input as preset data to the misaligned pixel number detection counter C1 through V. Here, the number of pixels that the sample row data deviates from the sample row data is counted and a φ7 signal is generated. The φ4 signal is created based on this φ7 signal, and the SCLK signal is increased by the number of pixels that are misaligned.
Pass to the clock input of down-counter C7. As a result, the counter C2 shifts the internal address in accordance with the amount of positional deviation, and corrects the scan start address to the location closest in phase to the current camera scan. clock φ
6. φ6 indicates a timing clock for replacing the corrected address with an internal address.

FIG. 9 shows an embodiment for actually generating clocks φ1 to φ6 based on the timing chart of FIG. 19. This clock generation circuit includes D-type flip-flops DFI to DF5, counters C4 and C5, and an inverter I.
Consists of NV.

5ZE from 5END signal with flip 70 knob DPI
By placing counters C4 and C5 in counting mode during the RO signal, clock φ2. Output φ3.

The clock φ3 is sent to the Noritsu block DF2. Clock φ1 is obtained by using it as an input of DF3. φ
1 is obtained by inverting φ3 with an inverter INV. Furthermore, the φ7 output of the counter C1 is transferred to the 7 lip-flop DF.
4. DF, the clock φ5. φ6 is obtained.

With the above-described configuration, even if the pattern of a printed matter is misaligned to some extent, it is possible to accurately determine whether the pattern is good or bad, enabling high-speed inspection and reducing the cost of the apparatus. Also, in order to compare the sample row data with the sample row data,
It is possible to perform a much more accurate inspection than when comparing patterns as a whole.

Furthermore, misalignment of printed matter in the running direction can also be dealt with by the circuit shown in FIG. 21, which is a partial modification of the determination circuit shown in FIG. 6. This is the judgment element JC, ~JC
7. Consists of shift registers SR1 to SR6 and a comprehensive judgment circuit TJU.

The shift register SR has a bit number equal to the sensor array bit number of camera 2 (Fig. 1), and the sample data SD
, the judgment level MD and the sample row data TD are delayed one pixel at a time like the latch in FIG.
The respective outputs of □ to JC7 ``1 to j7'' are given to the comprehensive judgment circuit TJU, and the minimum value is detected.

〔effect〕

As described above, the present invention compares sample row data with sample row data stored in memory in advance for each row.
One of these data is shifted from the other by an appropriate number of pixels and compared point by point with the other data, and the amount of positional shift between the two data when the level difference is the smallest is detected. Since the address of the one data is corrected according to the amount of positional deviation, the printer can be configured with a minimum amount of hardware to cope with the expected positional deviation of printed matter in the printing press conveyance system. Although the hardware is simple, highly accurate inspections can be performed in real time.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the configuration of an image information detection section of a pattern inspection device that is the object of the present invention, and FIG. 2 is a schematic explanatory diagram of sample pixel data and a recording method of sample pixel data for pattern inspection.
FIG. 3 is a characteristic diagram showing a method for a printed matter conveyance system and a pattern edge inspection method, FIG. 5 is a block diagram showing the configuration of an apparatus for implementing the method of the present invention, and FIG. 6 is an apparatus for the apparatus shown in FIG. 5. 7 is a block diagram showing a more specific configuration of the determination circuit in FIG. 6, and FIG. 8 is a block diagram showing a more specific configuration of the determination element in the determination circuit in FIG. 7. 9 is a block diagram showing a more specific configuration of the overall judgment circuit in the judgment circuit of FIG. 6, and FIG. A block diagram showing a more specific configuration of the low value detection circuit in the determination circuit, FIG. 11 is an explanatory diagram of the operation of the determination element identification circuit in the comprehensive determination circuit of FIG. 9, and FIG. A wiring diagram showing a specific configuration, FIG. 13 is a block diagram showing a more specific configuration of the judgment level setting circuit in the device of FIG. 5, and FIG. 14 is a proportional component setting circuit in the judgment level setting circuit of FIG. 13. FIG. 15 is an explanatory diagram of the widthwise positional deviation of printed matter in the printed matter conveyance system; FIG. 16 is an explanatory diagram of the image signal address correction operation of the camera in the apparatus of FIG. 5; 17th
18 is a block diagram illustrating a more specific configuration of the address correction circuit in the device shown in FIG. 5, and FIG. 18 is a timing chart of the signals of each part of the circuit in FIG. 18, the additional figure does not show the circuit that generates the clock used in the circuit in FIG. 18, and FIG. 21 is another example of the determination circuit in the device in FIG. 5. FIG. 1...Printed matter, 2...Camera, 3...Cylinder, 4
...Rotary encoder, 5, 7, 9, 17
...Sample pattern (sample nature) data, 6, 8, 10,
18...Specimen picture (specimen nature) data. TD...Sample row data, SD...Sample row data, M
D... Pixel control data, JC... Judgment circuit, JE...
... Judgment element, L... Latch, SR... Shift register, 'I'JU... Comprehensive judgment circuit. Applicant's agent Kiyoshi Inomata 6 Figure 1 Figure 2 Pixel location 4th field m - Pixel A device (me) Selfy A1 ■ 厘 Figure 18 1

Claims (1)

[Scope of Claims] 1. A pattern inspection method for printed matter in which pattern data extracted from a sample printed material is compared with pattern data previously extracted from the sample printed material and stored in a memory to determine the quality of the printed pattern. A plurality of pieces of data are formed by shifting the position of one of the sample line data detected line by line and the sample line data stored in the memory relative to the other nine by one pixel, and forming a plurality of pieces of data. Perform a level comparison between the sample row data and the sample row data using the data,
The positional deviation between the two pieces of data is determined from the positional relationship between the two pieces of data when the level difference becomes the minimum value, and the address of either of the two pieces of data is corrected based on this positional deviation amount. A pattern inspection method for printed matter, characterized by the following. 2. In a pattern inspection method for printed matter in which the quality of the printed pattern is determined by comparing pattern data extracted from the sample line data with pattern data previously extracted from the sample printed material and stored in memory, One of the detected sample row data and the sample row data stored in the memory is shifted in position relative to the other in units of one pixel to form a plurality of data, and this plurality of data is used to The level difference between the sample row data and the sample row data is compared, and the level difference is given as a fixed value, the sample row data is multiplied by a predetermined coefficient, and the concentration difference is expressed as a concentration difference in a part where the concentration suddenly changes. The quality of the pattern is judged based on its relationship to one judgment level selected from A pattern inspection method for a printed matter, characterized in that the address of either of the data is corrected based on the amount of positional deviation. 3. A device that generates a synchronization signal according to the conveyance operation of the printed material; a camera that scans the pattern of the printed material based on the synchronized signal to extract image information; and a camera that writes the image information extracted from the specimen printed material. One of the sample pixel data memory and a plurality of preset judgment levels is selected, and the level of image information for each pixel read from the sample pixel data memory is set and output based on the selected judgment level. a determination level setting circuit for determining image defects by comparing image information from the determination level setting circuit with image information of the sample print from the camera; and a determination circuit for determining image defects based on the output of the synchronization circuit. A pattern inspection device for printed matter, comprising an address correction circuit that forms a read address signal for a pixel data memory and corrects the address of the address signal based on the output of a determination circuit.