JPS6031245A - Semiconductor device - Google Patents

Abstract

PURPOSE:To increase the contacting area of a lead with a bump by forming the bump for one lead of a plurality of small bumps, thereby reducing the area of a recess part of the central portion of the bump at the plating time. CONSTITUTION:A photoresist 16 having approx. 40mum of pattern width is formed, and with the photoresist as a mask gold is plated to form two small bumps 7a, 7b. Since the width of the bump is approx. 40mum, a recess which occurs without approx. 20mum from the periphery of the bump at the plating time is regarded as almost non in a prindiple. Accordingly, a recess is not formed at the center of the bump. Thus, the bonding area of the lead of a lead frame with the bump after bonding the inner lead can be increased.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to the structure of a semiconductor device, and in particular, to the structure of a semiconductor device.
The present invention relates to the structure of a bonding pad of a semiconductor integrated circuit device R (IC) for tecL Bonding==TA11).

Currently, in order to improve the packaging density of ICs in devices such as nine large electronic devices, the 'l'AI3 method is being used instead of the conventional wire bonding method of bullet restraining IC cases and mounting IC cases on printed circuit boards. A method of mounting a plurality of IC pellets on a ceramic substrate according to the above method has been widely used. In addition, since the TAB method eliminates bonding,
It is also attracting attention in terms of reducing labor costs.

In the IC pellet used in this TAB method, the height of the bonding pad is set 20 to 30 mm above the substrate in order to maintain a clearance between the chip and the lead frame as an external electrode.
It is necessary to have a so-called bump structure with a height of μm.

1 to 3 are a sectional view and a top view showing the manufacturing process of a bump electrode according to the present invention. First, as shown in the cross-sectional view of FIG. 1(a), after a semiconductor element is formed in a semiconductor substrate l, a contact window is opened in a thin insulating film 2 on the surface, aluminum is deposited, and an internal wiring pattern is formed. and pad 3 is formed. Next, titanium 4 is deposited as an adhesive layer to the aluminum pad 3, and platinum 5 is deposited as a base metal layer for gold plating, thereby forming a bank pattern. This patterning usually employs a lift-off method using photoresist. Next, as shown in the cross-sectional view of FIG. 2 (al) and the plan view of FIG. Then, as shown in the cross-sectional view of FIG. Do a little bonding.

By the way, as shown in FIG. 2(a) and (+)), about 20 to 3
The central portion inside 0μn1 has a more depressed structure than the peripheral portion. This phenomenon is thought to be an etch effect during plating, and although the details of the cause are unknown, the more the plating solution deteriorates, the more pronounced this phenomenon becomes, and the difference in bump height between the center and periphery becomes larger. I know. If the lead frame structure is made of gold-plated copper, the bumps have a nickel-like structure, and the load during internal lead bonding can be increased. When the bumps are flattened, the bonding area between the bumps and the lead frame becomes larger, so bonding strength is not much of a problem. In the case of copper plated with tin, the bow/guing load must be small to prevent the melting of the gold in the bump and the alloy of 41J in the lead frame from falling off, and the depression in the bang will remain almost as it is, making it difficult to match the bump. This has the disadvantage that the bonding area of the lead frame becomes smaller and the bonding strength becomes smaller. However, if the height difference between the bumps is large, the plating straight edges must be defective (c), which has the disadvantage of lowering the yield of ICs.

The object of the present invention is to eliminate these drawbacks and provide a half-mounted re-mounting device with a bump voltage that provides sufficient bonding strength and improves the yield of ICs.

The =f-fatty cod 1d of the present invention has two or more bumps for one lead. ! 12100 small bump (about 40
By forming the bump with a width of μn1 (width 2), the area of the central corner of the bump during plating can be reduced, and the rocking surface of the lead frame lead and the bump after internal lead bonding can be There is a thick grass J'L-r.

Finally, the rudder will be explained according to an embodiment of the present invention.

FIGS. 4 to 6 to 1 are a sectional view and a plan view of an embodiment of the present invention and the manufacturing process. Figure 4 is the same as the conventional example, as shown in Figure 1. As shown in the cross-sectional view of FIG.
Gold plate 7 as a mask and make two small bumps 7a, 7.
form b. A plan view of this state 1 with 7 otoresists 16 removed is shown in Fig. 5 (bl). Fig. 5 (a)
, the width of the bump is about 40 t, as seen in (b)
lm, approximately 20 μm from the periphery of the bump during plating.
In principle, it can be said that there are almost no dents that occur within the bump area, so no dents will occur in the middle of the bump. That is, in general, l? from the periphery of the bump to the central corner.
If Ii 1ift is X, then the width of the small bump is within 2yK; It is possible to prevent dents from occurring at the center of the bump. Next, as shown in the plan view of IC57% (Ill), the photoresist 16 is removed, and then, as shown in the cross-sectional view of FIG. After dicing into individual pellets, the lead frame glue 9 and small bumps 7a,
7b and inner γX1 to lead bonding.

It can be seen that the bumps of the bump meter according to the present invention have almost no loose parts, and the bonding surface At between the leads of the lead frame and the bumps is large. Therefore, the bonding strength of the TiI4-IC can be sufficiently maintained, and
It is possible to improve the yield of wafers immediately after gold plating.

In addition, in the case of the first chestnut, the number of small bumps is two, but it is also possible to have more than two small bumps. An example of N'11 Pt was shown as the base metal A of the gold plate/fiber.
Pd.

Of course, even t-quaternary compounds such as Cr-Cl1 are not supported. In addition, although all the bumps were formed on aluminum using pellet internal wiring, they may also be formed on a 1111'4 edge film such as silicon nitride 1'A.

In this case, it is preferable to apply a thin gold plating to the bump and the inner wiring contact t, for example, Ill, -P, as an internal wiring fd pattern.

[Brief explanation of the drawing]

Figures 1 to 3 are β and 1 for explaining the manufacturing process of the bang electrodes of 1 and 1'' of Aki-Akushi. 1 is IF, 7th view,
HB 2 II (Ill is a plan view. No. 1 1
21 to 5 (Figure 5) This is a diagram for explaining the bump removal manufacturing process according to an embodiment of the present invention.
Figure, 'fd+5 1! ¥1 (a),'lis 6
L41 is a cross-sectional opening, and FIG. 5(b) is a plan view. 1...Semiconductor substrate, 2...Insulation i'-iL 3...Aluminum pad, 4...
...Titanium film, 5...Platinum film, 6.16.
...Photoresist, 7...Bump, 7
a, 7b...Small bump, 8...Bolly}' film, 9...Lead frame. Agent Attorney Uchihara July 1'゛）2 / Figure z 2 Figure z 3 Figure Z 4 Figure z 6 Figure

Claims (3)

[Claims] (1) In a semiconductor device having a bump electrode 4Ily,
A semiconductor device characterized in that the bump of the bump electrode is composed of a plurality of independent small bumps. (2) The semiconductor device according to claim 1, wherein the bumps are formed by a plating method. (3) The semiconductor device according to claim 2, wherein the bumps are formed by a gold plating method.