JPS603162B2 - Electric shutter device for cameras, etc. - Google Patents
Electric shutter device for cameras, etc.Info
- Publication number
- JPS603162B2 JPS603162B2 JP51108020A JP10802076A JPS603162B2 JP S603162 B2 JPS603162 B2 JP S603162B2 JP 51108020 A JP51108020 A JP 51108020A JP 10802076 A JP10802076 A JP 10802076A JP S603162 B2 JPS603162 B2 JP S603162B2
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- transistor
- current
- emitter
- darlington connection
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Landscapes
- Exposure Control For Cameras (AREA)
- Shutter-Related Mechanisms (AREA)
- Amplifiers (AREA)
Description
【発明の詳細な説明】
本発明はカメラ等に用いる電気シャツタ回路特に亀流変
換回路に特徴を有するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention is characterized by an electric shutter circuit used in a camera or the like, particularly a turtle current conversion circuit.
従釆のこの種電気シャツタ回路における電流変換回路は
その一例を第1図に示す如く、調定惜織出力部1からの
フィルム感光度値及び認定絞り値等に応じた電気信号出
力とフオトダィオードSBCにより感知した被写界の明
るさに応じた電気信号出力とを頚9光演算回路A,で演
算し、その総合出力を制御情報としてトランジスタT2
に与え、該トランジスタT2に前記情報に応じた鰭流l
oが流れるようになし、このトランジスタT2のコレク
タ電流loをPNPトランジスタT3,T4からなる電
流変換回路でもつて電流lcに変換し、該電流lcでも
つて積分コンデンサC,を充鰭するように構成し、タイ
ミングスイッチSの開放による調時動作開始時から該コ
ンデンサCTの前記充電による端子間電圧が一定値まで
上昇した際に、これを感知してスイッチング回路A2が
動作し、調時値決定時期を機械信号に変えるマグネット
Mを駆動するようになしてある。そこで、このような電
気シャツタ回路特に前記亀流変換回礎をIC化しようと
する場合に、このような従来の電気シャツタ回路では、
lqヒによるPNPトランジスタに起因する次の欠点が
生じる。An example of the current conversion circuit in this type of electric shutter circuit is shown in FIG. 1, which outputs an electric signal from the adjustment output section 1 according to the film sensitivity value and the certified aperture value, and outputs an electric signal from the photodiode SBC. The electric signal output corresponding to the brightness of the subject sensed by the neck 9 optical calculation circuit A is calculated, and the total output is used as control information to be sent to the transistor T2.
, and the transistor T2 is given a fin flow l according to the information.
The collector current lo of the transistor T2 is converted into a current lc by a current conversion circuit consisting of PNP transistors T3 and T4, and the integrating capacitor C is charged with the current lc. , when the voltage between the terminals due to the charging of the capacitor CT rises to a certain value from the start of the timing operation by opening the timing switch S, this is sensed and the switching circuit A2 operates to determine the timing for determining the timing value. It is arranged to drive a magnet M which is converted into a mechanical signal. Therefore, when attempting to integrate such an electric shatter circuit, particularly the turtle current conversion circuit, in such a conventional electric shatter circuit,
The following drawbacks arise due to the PNP transistor due to lq.
即ち、先ずPNPトランジスタはその電流増幅率(ェミ
ツタ接地)hfeが低い(第3図上特性曲線1,図示)
。That is, first of all, the current amplification factor (grounded emitter) hfe of the PNP transistor is low (characteristic curve 1 in Figure 3, shown).
.
その為に、電流1。の変換電流lcにトランジスタT4
のベース電流による影響が生じ易い。今、lo=183
十lc3十184…・・…・【1}IC=hfe401
84………‘21そして、トランジスタT3とLとの特
性が等しいとすれば、lc3=lc,IB3;IB4,
hfe3ニhに4 ………糊であるから、前記{11式
は1。For that, the current is 1. The conversion current lc of transistor T4
This is likely to be affected by the base current. Now, lo=183
10lc3 184...[1}IC=hfe401
84......'21 Then, if the characteristics of transistors T3 and L are equal, lc3=lc, IB3; IB4,
hfe3 ni h to 4......Since it is a glue, the above formula {11 is 1.
i農+1C十髭.........‘41となり、lo
hにIC=・十h言e=h席軒32‐10……
…{5}となる。i Agriculture + 1C Ten Beard. .. .. .. .. .. .. .. .. '41 and lo
h to IC = 10h word e = h seat house 32-10...
...{5}.
そこで、変換電流lcが電流loに比例するためには、
h栓》2であることが必要であり、好ましくは電流変換
回路における変換素子のh笹が出来るだけ高いことが望
ましい。Therefore, in order for the converted current lc to be proportional to the current lo,
It is necessary that the height of the conversion element in the current conversion circuit is as high as possible.
このことは、例えば調時値を1/2000secからS
ec程度迄変化させたい場合に、電流lcをlmAから
10仇A程度変化させる必要があり、第3図上1,特性
曲線図示のPNPトランジスタでは、lc:10皿Aで
はhfe=10であるので、hね前証5’式はlc=h
柿;32・lo=0.89oとなる。This means that, for example, the timing value can be changed from 1/2000 sec to S
If you want to change the current to about ec, it is necessary to change the current lc from lmA to about 10A, and in the PNP transistor shown in the characteristic curve 1 in Figure 3, hfe = 10 when lc is 10A. , h The previous proof 5' formula is lc = h
Persimmon: 32・lo=0.89o.
lc=100山Aではhfe=斑であるので、前記【5
}式からlc=0.97らとなり、電流loに比例して
変換電流lcが変化しない。次に、PNPトランジス外
まコレクタ電流が大きくなるとlc−VBE特性の直線
性が陣われる(第34図上点線図示部分)。図示の如く
、例えばlc=30山A程度で直線性が悪くなるために
、トランジスタT3とT4との特性がわずかに異なると
、電流が多くなるに従って電流loとlcとが比例しな
くなる。実際にはlc=lmAでは誤差が多くて実用3
に供し得なくなり、結果的に、この種トランジスタによ
る回路のIC化は不可能となる。本発明の目的は前述し
た問題を解決することができるカメラ等における電気シ
ャツタ装置を提供することにある。In lc = 100 mountains A, hfe = spots, so the above [5
} From the formula, lc=0.97, etc., and the converted current lc does not change in proportion to the current lo. Next, when the collector current outside the PNP transistor becomes large, the linearity of the lc-VBE characteristic becomes sharper (the part shown by the dotted line in FIG. 34). As shown in the figure, for example, when lc=30 peaks A, the linearity deteriorates, so if the characteristics of transistors T3 and T4 are slightly different, as the current increases, the currents lo and lc will no longer be proportional. In reality, when lc=lmA, there is a lot of error and it is practically used.
As a result, it becomes impossible to integrate a circuit using this type of transistor into an IC. SUMMARY OF THE INVENTION An object of the present invention is to provide an electric shutter device for a camera or the like that can solve the above-mentioned problems.
夕前記目的を達成するために、
本発明によるカメラ等における電気シャツタ装置は、N
PNトランジスタT42のベースにPNPトランジスタ
T32のコレクタを接続した第1のダーリントン接続回
略と、前記PNPトランジスタT32のベース・ェミッ
タ間に後続されたダイオード接続のトランジスタからな
る前記ダーリントン接続回路のバイアス回路T31と、
脚光演算回磯〔S8CA,〕と、前記バイアス回路T3
1と直列に接続されカソードが前記トランジスタT42
のェミツタに接続されているダイオードT41と、前記
側光演算回路〔SBCへ〕の出力電圧がベースに接続さ
れコレクタから前記バイアス回路T31と前記ダーリン
トン接続回路に被写体の明るさに応じたコレクタ電流l
oを供給するNPNトランジスタT2と、前記ダーリン
トン接続回路と同等な回路でPNPトランジスタT34
のベース・ェミッタが前記バイアス回路T31に接続さ
れ、NPNトランジスタT44のベースが前記PNPト
ランジスタT34のコレクタに接続されている第2のダ
ーリントン接続回路と、前記NPNトランジスタT44
のェミッ夕と前記NPNトランジスタT2のェミッタ間
に接続されている積分コンデンサCTとからなり、前記
積分コンデンサCTに前記電流loに比例した充電電流
lcを供V給するように構成されている。前記構成によ
れば、被写体の明るさに応じた電流は、直線性の良いN
PNトランジスタに供給される。そしてNPNトランジ
スタのコレクタを前記NPNトランジスタのベースに接
続することによって直線性は改善される。被写体の明る
さに応じた電流をPNPトランジスタによって流すとP
NPトランジスタはh笹が低いため直線性が損なわれる
と言う問題は完全に解決できる。In order to achieve the above purpose,
The electric shutter device in a camera or the like according to the present invention has N
a bias circuit T31 of the Darlington connection circuit consisting of a first Darlington connection circuit in which the collector of a PNP transistor T32 is connected to the base of the PN transistor T42; and a diode connection transistor connected between the base and emitter of the PNP transistor T32; and,
The spotlight calculation circuit [S8CA,] and the bias circuit T3
1 and whose cathode is connected in series with the transistor T42.
The diode T41 connected to the emitter and the output voltage of the side light calculation circuit [to SBC] are connected to the base, and the collector current l is connected to the bias circuit T31 and the Darlington connection circuit according to the brightness of the subject.
o, and a PNP transistor T34 in a circuit equivalent to the Darlington connection circuit.
a second Darlington connection circuit in which the base and emitter of the NPN transistor T44 are connected to the bias circuit T31 and the base of the NPN transistor T44 is connected to the collector of the PNP transistor T34;
and an integrating capacitor CT connected between the emitter of the NPN transistor T2 and the emitter of the NPN transistor T2, and is configured to supply a charging current lc proportional to the current lo to the integrating capacitor CT. According to the above configuration, the current according to the brightness of the subject is N with good linearity.
Supplied to the PN transistor. The linearity is then improved by connecting the collector of the NPN transistor to the base of the NPN transistor. When a current corresponding to the brightness of the subject is passed through a PNP transistor, P
Since the NP transistor has a low h-value, the problem of loss of linearity can be completely solved.
以下図示の実施例に付いて詳述する。The illustrated embodiment will be described in detail below.
第2図示の本発明装置の実施回路において、従来の第1
図示回路と共通な回路素子及び機能部には夫々同一記号
を附してあり、その他、制御情報に応じた電流1。In the implementation circuit of the device of the present invention shown in the second figure, the conventional first
Circuit elements and functional parts common to the illustrated circuit are given the same symbols, and other currents 1 according to control information.
を流す回路を、ダイオード接続のトランジスタT31と
ダイオードT41との直結回路とPNPトランジスタT
32及びNPNトランジスタT42のダーリントン接続
回路であって前記直結回路の中点から制御入力を受ける
回路とによって構成してあり、他方、変換電流lcを流
す回路PNPトランジスタT33及びNPNトランジス
タT43からなるダーリントン接続回路とPNPトラン
ジスタT34及びNPNトランジスタT44からなるダ
ーリントン接続回路とを並列嬢続した構成であって共に
前記中点からの制御入力を受けるように構成してある。
このような構成よりなる本発明装置では、その作動時に
、制御情報に応じた電流loは10=1C42十1C3
2十1832十IC31十1831・….・.・・【6
1又、変換電流lcは
1Cニ1C44十1C34十1C43十IC33 .
........■となり、PNPトランジスタの特性
が互に等しく、同じくNPNトランジスタの特性が互に
等しいとすれば、hfe42=hfe43=h企44己
hfe4 相当lc3・=lc32=lc33コlc3
4…lc8 相当 …【1脚=1832;IB33:
IB34三1B3相当=憲ノ1C42=1C43:1C
44三IC4相当号又、,C3=憲・・側
となるから、【6’,‘7’,‘8’,■式より、lc
=2(lc3十lc4)=21。The circuit that allows the flow of
32 and a Darlington connection circuit consisting of an NPN transistor T42, which receives control input from the midpoint of the direct connection circuit, and a Darlington connection circuit consisting of a PNP transistor T33 and an NPN transistor T43 through which a conversion current lc flows. The circuit is connected in parallel to a Darlington connection circuit consisting of a PNP transistor T34 and an NPN transistor T44, both of which are configured to receive control input from the midpoint.
In the device of the present invention having such a configuration, during operation, the current lo according to the control information is 10=1C42+1C3
21,832, IC31, 1,831...・.. ... [6
1. Also, the converted current lc is 1C 2 1C44 1C34 1C43 1C33 .
.. .. .. .. .. .. .. .. ■If the characteristics of the PNP transistors are equal to each other and the characteristics of the NPN transistors are also equal to each other, then hfe42=hfe43=h44hihfe4 Equivalent lc3・=lc32=lc33kolc3
4...equivalent to lc8...[1 leg = 1832; IB33:
IB34 three 1B3 equivalent = Kenno 1C42 = 1C43:1C
443 IC4 equivalent number Also, , C3 = Constitution... side, so [6', '7', '8', ■From the formula, lc
=2(lc30lc4)=21.
・〔(lc4十lc3 )/くIC4十21C3十21
&)〕=2L・〔(h艦十1)/(hfe4十2十2/
hfe3)〕 ・・・・・・・・・OUよって、h
fe4>>2であるならばlcはloに比例する。例え
ば、lc=10仇AではNPNトランジスタのhfe=
70であるので(第3図上特性曲線12図示)、前記(
11)式はlc=0.972×lolc=100ムAで
はhfe4=170であるので、前記(11)式より1
。・[(lc4×lc3)/kuIC4×21C3×21
&)]=2L・[(h-ship 11)/(hfe4-12-2/
hfe3)] ......OU, h
If fe4>>2, lc is proportional to lo. For example, when lc=10A, hfe=
70 (Characteristic curve 12 shown in Figure 3), the above (
11) Equation is lc = 0.972 x lolc = 100 μA, hfe4 = 170, so from equation (11) above, 1
.
=0.受粉×2Lであって、これは前記従来装置におけ
る鰭流loとlcとの関係に比べて、本発明装置におけ
る母流loとlcとの比例関係が大いに改善されたこと
が判かる。=0. Pollination×2L, which indicates that the proportional relationship between the mother flow lo and lc in the device of the present invention is greatly improved compared to the relationship between the fin flow lo and lc in the conventional device.
又、PNPトランジスタT13,T32.T33及びT
34に流れる電流は従来装置において毒讐相当であるの
で・IC=1Mの技大軍流時でもPNPトランジス外こ
流れる電流はhfe4=200(atlc4=500山
A)として、lc3=2.5ムA相当であり、その結果
、本発明菱直における前記PNPトランジス外こは比較
的小電流が流れるので、この小電流域では第4図に示す
如くそのVB8−lc特性の直線性を保っている範囲で
あるので、従釆装置におけるPNPトランジスタにおけ
る前記特性の非直線的による電流loとlcとの比例関
係の乱れを、本発明装置では改善し得た。Moreover, PNP transistors T13, T32 . T33 and T
Since the current flowing through 34 is equivalent to a poisonous enemy in the conventional device, the current flowing outside the PNP transistor even when IC = 1M is the same as the current flowing through the PNP transistor is hfe4 = 200 (atlc4 = 500 mountain A), and lc3 = 2.5 μA. As a result, a relatively small current flows through the PNP transistor outer coil of the present invention, so that in this small current range, the linearity of the VB8-LC characteristic is maintained as shown in Fig. 4. Therefore, the device of the present invention can improve the disturbance in the proportional relationship between the currents lo and lc due to the non-linear characteristics of the PNP transistor in the slave device.
このように本発頚装置は従来装直における電流変換回路
の変換特性を極めて良く改善することが出釆、この回路
のIC化に充分に供し縛るものであり、しかも変換電流
回路に負荷抵抗Rを挿入することによって変換電流を容
易に検出することが出来て、電流制限部への附設を容易
に行うことの出釆る副次的効果をも有するものである。In this way, the present device is capable of extremely improving the conversion characteristics of the current conversion circuit in conventional mounting, and is fully applicable to the conversion of this circuit into an IC. By inserting the converter, the converted current can be easily detected, and it also has the secondary effect of being easily attached to the current limiting section.
図面の簡単な説明第1図は従来の電気シャツタ回路にお
ける電流変換回路の一例を示す回路図、第2図は本発明
袋鷹の実施例を示す回路図、第3図はPNP及びNPN
トランジスタのh笹特性図、第4図はPNP及びNPN
トランジスタのVB耳一1c特性図である。Brief Description of the Drawings Fig. 1 is a circuit diagram showing an example of a current conversion circuit in a conventional electric shirtter circuit, Fig. 2 is a circuit diagram showing an embodiment of the present invention Fukurotaka, and Fig. 3 is a circuit diagram showing an example of a current conversion circuit in a conventional electric shirtter circuit.
Transistor h-sasa characteristic diagram, Figure 4 is PNP and NPN
FIG. 3 is a characteristic diagram of the VB terminal 1c of a transistor.
T,〜44・・・・・・トランジスタ又はダイオード、
SBC・・・・・・フオトダィオード、CT・・・・・
・時定用のコンデンサ、R……負荷抵抗、ん……洩り光
演算回路、A2・”…スイッチング回略、M……マグネ
ット、1。・・・・・・制御情報に応じた電流、lc・
…・・変換電流。第1図
第2図
第3図
第4図T, ~44...transistor or diode,
SBC...Photodiode, CT...
・Capacitor for time setting, R...Load resistance, N...Leakage light calculation circuit, A2...Switching circuit, M...Magnet, 1...Current according to control information, lc・
...Conversion current. Figure 1 Figure 2 Figure 3 Figure 4
Claims (1)
ジスタT32のコレクタを接続した第1のダーリントン
接続回路と、前記PNPトランジスタT32のベース・
エミツタ間に接続されたダイオード接続のトランジスタ
からなる前記ダーリントン接続回路のバイアス回路T3
1と、測光演算回路〔SBCA_1〕と、前記バイアス
回路T31と直列に接続されカソードが前記トランジス
タT42のエミツタに接続されているダイオードT41
と、前記測光演算回路〔SBCA_1〕の出力電圧がベ
ースに接続されコレクタから前記バイアス回路T31と
前記ダーリントン接続回路に被写体の明るさに応じたコ
レクタ電流I_oを供給するNPNトランジスタT_2
と、前記ダーリントン接続回路と同等な回路でPNPト
ランジスタT34のベース・エミツタが前記バイアス回
路T31に接続され、NPNトランジスタT44のベー
スが前記PNPトランジスタT34のコレクタに接続さ
れている第2のダーリントン接続回路と、前記NPNト
ランジスタT44のエミツタと前記NPNトランジスタ
T_2のエミツタ間に接続されている積分コンデンサC
Tとからなり、前記積分コンデンサCTに前記電流I_
oに比例した充電電流I_cを供給するように構成した
カメラ等における電気シヤツタ装置。[Claims] 1. A first Darlington connection circuit in which the collector of the PNP transistor T32 is connected to the base of the NPN transistor T42;
Bias circuit T3 of the Darlington connection circuit consisting of a diode-connected transistor connected between emitters
1, a photometric calculation circuit [SBCA_1], and a diode T41 which is connected in series with the bias circuit T31 and whose cathode is connected to the emitter of the transistor T42.
and an NPN transistor T_2 whose base is connected to the output voltage of the photometric calculation circuit [SBCA_1], and whose collector supplies a collector current I_o according to the brightness of the subject to the bias circuit T31 and the Darlington connection circuit.
and a second Darlington connection circuit, which is a circuit equivalent to the Darlington connection circuit, in which the base and emitter of the PNP transistor T34 are connected to the bias circuit T31, and the base of the NPN transistor T44 is connected to the collector of the PNP transistor T34. and an integrating capacitor C connected between the emitter of the NPN transistor T44 and the emitter of the NPN transistor T_2.
T, and the current I_ to the integrating capacitor CT.
An electric shutter device for a camera or the like configured to supply a charging current I_c proportional to o.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP51108020A JPS603162B2 (en) | 1976-09-09 | 1976-09-09 | Electric shutter device for cameras, etc. |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP51108020A JPS603162B2 (en) | 1976-09-09 | 1976-09-09 | Electric shutter device for cameras, etc. |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5333122A JPS5333122A (en) | 1978-03-28 |
| JPS603162B2 true JPS603162B2 (en) | 1985-01-26 |
Family
ID=14473932
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP51108020A Expired JPS603162B2 (en) | 1976-09-09 | 1976-09-09 | Electric shutter device for cameras, etc. |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS603162B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0369568U (en) * | 1989-11-13 | 1991-07-10 |
-
1976
- 1976-09-09 JP JP51108020A patent/JPS603162B2/en not_active Expired
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0369568U (en) * | 1989-11-13 | 1991-07-10 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5333122A (en) | 1978-03-28 |
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