JPS603226B2 - microcomputer system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a microcomputer system, and particularly to its signal output method.

Recently, the use of microcomputers has been increasing to meet the demands for low cost, small size, and high reliability of equipment.
Along with this, demands for microcomputers that go beyond basic performance have come to be made.

In particular, requirements such as speed, number of input/output ports, and synchronization of multiple output signals are critical aspects of microprocessors and have been difficult to meet. For example, the first
In the conventional example shown in the figure, when expanding a 4-bit output signal to 8 bits, an external latch circuit is required, an additional 2-bit output port is required as a latch signal, and the time required to complete the output is more than 4 times as long. However, the two latch circuits cannot guarantee output synchronization.

In order to solve such problems, the present invention provides two improvements to conventional circuits.
By simply adding ~3 circuits, we were able to shorten the time required from detecting a certain state to outputting a response, expand the number of output ports, and achieve synchronization.

An embodiment of the present invention will be described below with reference to FIGS. 2 to 4.

FIG. 2 is a block diagram of the microcomputer system of the present invention.

First of all, a microprocessor has an external program memory, an address bus for program access,
The data bus and input/output ports are separate and independent, the output port is 4-bit parallel, the program is configured in 1 word = 8 bits, the external program area is PROM (IK x 8 bits), and the remaining part of PROM (address 'Bait 8~
Assume that X′ helmet F) can be used as a table area.

Further, it is assumed that the current target output port is an 8-bit signal, and there are only 8 states and combinations of the 8 bits, and simultaneity is required for ON and OFF. It is also assumed that the CPU outputs an address, takes in and decodes an instruction, and executes an instruction during one instruction cycle as shown in FIG. The clock signal generation circuit 2 is composed of a flip-flop, and is cleared when the CPU clock signal e is high, and is set at the rising edge of the signal d (most significant bit E3 of the output port E).

The output clock signal f is the PROM address switching circuit 3.
and is supplied to the latch circuit 5. The PROM address switching circuit 3 uses the clock signal f to select the normal address a (10 bits) from the microprocessor and the output port E.
Switch the PROM table area address b (lower 3 bits EO to E2 of output port E) issued from PR
Outputs OM address c. PROM for program storage
4 has a program area (IK×8 bits), and normally the last several bytes to several tens of bytes remain unused. The part of the unused area (address X' is 8 to
'Snake F) is used as a table area. Latch circuit 5
latches the data bus information g using the output signal f of the clock signal generation circuit 2 and outputs it as OUTO to OUT7. Now, if it is necessary to simultaneously change the states of control outputs OUTO to OUT7 immediately in response to the occurrence of an external interrupt, the table area from output port E where the microprocessor (CPU) is located to EO to E3 = ''111r. Output address signal.

Then, as shown in FIG. 4, the signal d (E3) becomes High, and the output f of the flip-flop of the clock signal generation circuit 2 becomes High, and the address switching circuit (
3), EO to E2 are replaced with the lower 3 bits of address bus a, the 4th bit and above become "1", and PRO
X' helmet F of M is addressed, and its content "100011101'1" is output to data bus g.At this time, clock signal f (CLK) = High causes latch circuit 5 to
The contents of the data bus g are latched to OUT~O.
Output as UT7. Under these conditions, the CPU clock signal e becomes the Hi-axis and the signal f is reset, so that the next instruction is executed normally. Note that the signal d (E3) needs to be set to Low once before changing the states of OUTO to OUT7. Furthermore, some microprocessors output a pulse signal for external latch when outputting a specific port, but in that case, the 4 bits of that output port are PR
Fully available for accessing the OM table space, 16
The output state up to the weight can be selected, and the clock signal generation circuit 2 can be omitted. With the above configuration, the present invention can reduce the output response time of the microcomputer, improve the synchronization of output signals, expand the output port, and effectively utilize the remaining memory.

[Brief explanation of drawings]

Fig. 1 shows a conventional example in which a 4-bit output signal is expanded to an 8-bit output signal using two latch circuits, Fig. 2 is a block diagram of a microcomputer system according to an embodiment of the present invention, and Fig. 3 is a diagram showing the address switching circuit 3 of FIG. 2,
FIG. 4 is a diagram showing a timing chart of the embodiment of FIG. 2. 1... Microprocessor (CPU), 2.・．． Clock signal generation circuit, 3... PROM address switching circuit, 4... PROM for program storage, 5... latch circuit. Figure 1 Figure 2 Figure 4 Figure 3

Claims (1)

[Claims] 1. In a microcomputer system that has an external program memory separate from the central processing unit CPU, and in which an address bus, a data bus, and an input/output port for program access are separated and independent, the program memory has, in addition to the program area, In the remaining part not used as the program area, a table area is provided to store information with a larger number of parallel bits than the number of parallel bits of the CPU output port and needs to be output at the same timing. A microcomputer system comprising an address switching circuit for accessing a table area using address information output from an output port of a CPU when necessary, and a latch circuit for latching information on a data bus at that time. .