JPS60329A - distance measuring device - Google Patents

Abstract

PURPOSE:To speed up measurement by removing a DC signal level included in an output from a photodetecting element from the output when the DC signal level is larger than a prescribed value. CONSTITUTION:An output from an OP amplifier which is determined is accordance with the direction of current flowing into a feedback system 46 is detected by a comparator 52 to discharge a capacitor 48. The charging potential of the capacitor 48 is determined so that the output current (DC signal component) of a PSD 45 is made equal to a current value of current flowing into a current mirror (f) (a current value of current flowing into the feedback system 46 is zero). Even when large current is sent from the PSD 45, the DC signal from the PSD is flowed into a current mirror circuit to remove the DC signal from the PSD output and prevent the amplifier in the initial stage from being saturated.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a distance measuring device for a camera, particularly an active method in which distance measuring information is obtained by projecting light from a light projecting means onto a subject and receiving the reflected light without using any movable members. The present invention relates to a distance measuring device.

In conventional active distance measuring devices, the light emitting element that projects infrared light from the camera body towards the subject is moved in conjunction with the movement of the photographic lens in the optical axis direction (extending operation). A focusing operation (distance adjustment operation) is performed by extracting infrared light reflected from an object by a light receiving element, and stopping movement of the photographing lens when the output reaches a maximum. However, since this method performs distance measurement at the same time as the photographic lens moves, it is not suitable for prefocusing, which obtains distance measurement information before the shutter release, and also requires mechanical components to drive the light emitting element, etc. Therefore, we needed more space.

In view of this point, in recent years, a method using a semiconductor device detector PSE has been proposed as a method for directly obtaining distance measurement information from the relationship between two signal outputs extracted from a light receiving element.
44809, and a method using two light receiving elements was proposed in Japanese Patent Publication No. 49731/1983. However, in this method, in order to increase the resolution of the output corresponding to the distance to a certain extent, it is necessary to increase the area of the light receiving part, and the current generated by background light becomes large at high brightness, and the first stage amplifier becomes saturated. Otherwise, the signal output may not be detected.

The present invention has been made in view of this point, and includes a light projecting element that projects pulse-modulated signal light to a subject, and a light receiving element that receives reflected light from the subject due to the light projecting operation of the light projecting element. and a processing circuit that detects a subject distance based on the light receiving element output, a detection circuit that detects a DC signal level included in the light receiving element output, and a DC signal level detected by the detection circuit. a DC signal suppression circuit that removes a signal level from the output of the light receiving element; and when the DC signal level detected by the detection circuit is larger than a predetermined value, the signal suppression circuit cancels the DC component; By preventing saturation of the first-stage amplifier and performing signal processing immediately without performing the above-mentioned suppression operation when the brightness is low, the time required for the signal suppression operation in the ranging operation process can be shortened, and the distance measurement operation can be performed quickly. This is what was done.

Hereinafter, a distance measuring device according to the present invention will be explained.

FIG. 1 shows a cross-sectional view of a semiconductor device detector PSD as a light-receiving element used in this embodiment. A photocurrent is generated in accordance with the counter electrode arm, E), and a signal current of -9 given by the following equation (I) is output as a position signal. Now, calculate the distance between the output electrodes M and B of the PSD, and let the distance from the poles to the light receiving point be X. Since the surface of the PSD is a uniform resistor, the following relationship is established), and therefore the signal current The light receiving point X can be obtained from the relationship from A+. Therefore, according to the N principle of triangulation, if the light receiving point is located at a predetermined position on the surface of the PEID according to the distance to the object, the distance from the above-mentioned X to the object can be measured.

In other words, it is necessary to control the engineering (=from engineering A0) to a constant level,
It is possible to directly correspond the absolute value of either A or 1 to distance X, and from the correspondence between X and subject distance, M or 1 directly represents the subject distance, so it is possible to detect A or 1B. Distance measurement can be performed by doing this. In FIG. 1, when one of the counter electrodes B is opened, all of the photocurrent generated on the light receiving surface is emitted from the other electrode. Therefore, in this embodiment, it is necessary to open one output to obtain the sum total of the light-generated current from the direction of the output, and furthermore, to bias one output to the reference level, it is necessary to open the output em or The configuration is such that distance measurement information is obtained only from the output value of one side.

FIG. 2 is a circuit diagram showing an embodiment of the distance measuring device according to the present invention.

In the figure, 45 is P13 as a light receiving element shown in the first figure.
In D, the PEID is 1REiD103 as a light projecting means.
There is no way that the light reflected from the object by the light emitted from the 1R base D 103 is received through the light receiving lens located at a base line distance from the light emitting axis. Therefore, the light-receiving point on the surface of the light-receiving element PsD corresponds to the object distance, and when the terminal B is opened, the output from the terminal is the same as that of the above-mentioned terminal A1, and when the transistor 41 is turned on, Terminal A when terminal B is biased with reference level
The output from the above-mentioned process A becomes an output signal corresponding to the subject distance.

47 is an operational amplifier (hereinafter referred to as a comparator constituting a detection circuit that detects the installed DC component) that detects the received light output; f and d are current mirror circuits; a and e are constant current sources; 48 is a capacitor; 49 is PET, and these circuit elements constitute a DC signal suppression circuit. 200 is a comparator 120 that detects the output of the OP amplifier 47.
Reference numeral 1 denotes an RSS flip-flop, which controls the operation of the suppression circuit and constitutes a discrimination circuit. 75, 80
.

83.87, 91, 101 is OP Ang, 76.77.
95 is an analog switch, 79, 82, 100 is a capacitor, 72-74.7B, 81.84, 85, 86,
88, 89, 90, and 96 are resistors, and these K constitute a distance measurement processing circuit.

102. 106, 119, 115 are transistors, g
is a constant current source, 105 is an op7y amplifier, 104, 107, 1
14,116°117.120,121 is resistance, 108
is a capacitor, and with these, 1RED 103
Configures the lighting drive circuit.

1 is a power switch, 2 is a power supply, 3 is a reference voltage generation circuit,
4, 5, and 6 are resistors, capacitors, and inverters that constitute the power-up clear circuit. 7 is a pulse generation circuit that generates clock pulses for controlling a sequence control circuit section to be described later, and a is a Johnson counter.

The logic elements, flip-flops, counters, etc. indicated in the middle of FIG. 2 are circuit elements that together with the Johnson counter constitute a sequence control circuit section for sequentially controlling the distance measuring operation.

Next, the operation of the second illustrated embodiment will be explained.

First, when the power switch 1 is turned on, power is supplied from the power source battery 2 to each circuit. A reference voltage KVC is generated from the reference voltage generation circuit 3 and applied to each terminal, and the initial reset pulse TRPVC from the power-up clear circuit consisting of a resistor 4, a capacitor 5, and an inverter 6 is applied to the D-7. Lip 70gB, 9.10 is initially reset. At the same time, the TRPVC resets the Re flip-flop 13 via the impark 14, and its output Q generates the pvc signal, and the D-7 flip-flop p-horns 11 and 12 are initially reset by the output enable. Here, the D-7 lip-flops 8, 9, 10°11.12 form a Johnson counter a.

The PVC signal resets the Re flip-flop 26.28.31.97, 201, and the output Q of the Re flip-flop 13 resets the binary counter 18 via the OR gate 15. The output Q6 of the binary counter is the output Q of the D-flip-flop 12 applied to its input terminal divided by 26, and Q7 is 2'
, Q, , is 2B , Q, is 29°Q10 is 210
Each is a frequency-divided output. Initial reset R8
Q output A of 7rip 70ug97, FSTli low level (hereinafter referred to as L level, 1t-0), so NAND
The output state of the gate 19 becomes high level /I/ (hereinafter referred to as R level), and the q output OP of the Re flip-flop 20
]lfM becomes L level. The opxN output is inverted by the inverter 67, the output becomes R level, and the resistor 58
, 39 to the transistor 40, which turns on. transistor 4
3, 44, and the current from the constant current source formed by the resistor 42 is absorbed by the transistor 40, so the transistor 41 is turned off), and one side terminal B of the PSD 45 as a light receiving element shown in the first figure is open. Become. As a result, all of the photocurrent (current generated by background light) generated in the PAD (from M1 described in FIG. 1) flows toward the OP amplifier 47, and the current also flows through the feedback system 46. Due to the voltage drop there, the output of the OF amplifier 47 becomes lower than the reference voltage XVC. This output is applied to comparators 52 and 200, each with a KVC.

α (lower predetermined potential than XVC) is input. Now, assume that the current from the AJ5 PSD becomes large under high brightness, and as a result, there is a risk that the OP amplifier 47 may ratte down. In this state, the output of the OP amplifier 47 is as low as the level of the comparator 200.
The output of the comparator 200 is at the L level (J), and the Q output DOWIJ of the RS flip-flop 201 is at the fifth level. Further, the output of the comparator 52 also becomes L level. Here, since the Q output of the Re flip-flop 28 reset by the pvc signal is UH level, the output ASWON of the AND 202 is R and becomes a level due to the relationship with the DOWN output, and as a result, the output of the AND gate 69 is L level, and the NAND gate The output of 68 also becomes L level. AND
The output of 69 is connected to transistor 5 via resistor 57.58.
6, this turns on and supplies all the current to the constant current source C formed by resistor 63, transistors 62, 64, and transistors 53, 54 .
No current flows through the current mirror circuit d formed by transistor 55, and the collector output of transistor 53 becomes an oven. Also, the output of the NAND gate 68 is connected to the resistor 66.67.
is applied to transistor 65 through resistor 59, transistor 60.
The constant current source θ formed by 1 operates, and the current charges the capacitor 48 in a negative direction with respect to the power supply voltage Vcc.

As the charge increases, the source-gate voltage of P-MOB transistor 49 increases, and the current flowing out from the drain increases, and the current flows through transistor 50.
51 , and the output of current mirror f is connected to one terminal of PAD 45 . As a result, the current generated from the light receiving element 45 is gradually sucked into the current mirror f. On the other hand, when the current sucked by the current 2- increases, the output of the OF amplifier 47 rises above KVC through the feedback 46, and the output of the comparator 52 becomes H level. The outputs of NAIJD 6 B and AND6-9 are both at H level, and the constant current source θ loses its function due to the transistor 65 being turned on, and the transistor 56 is being turned off, so the current of the constant current source C is a current mirror d. flows through the capacitor 48, discharging the capacitor 48. As a result, P-
The voltage between the source and gate of the MOB becomes smaller, and the current flowing through the current mirror f gradually decreases. By constantly applying feedback to the entire circuit in this way, the current flowing through the feedback system 46 of the p/op amplifier 47 approaches zero, and the large current flowing from the PSD (back!
This prevents the first stage amplifier from becoming saturated when the brightness is high. That is, the comparator 52 detects the output of the OF amplifier 47, which is determined according to the direction of the current flowing in the feedback system 46, and discharges each discharge to the capacitor 48. The charging potential of the capacitor 48 is determined so that the current value flowing through the fi FED becomes the same value (the current value flowing through the feedback system 46 at this time is zero). The DC signal from the PAD is passed through a current mirror circuit, and the DC signal is removed from the PSD output to prevent the first-stage amplifier from being saturated.

Further, the Johnson counter a has been operating since the power was turned on, and the counter 18 counts the output pulses of the Johnson counter.

Therefore, after a certain period of time has elapsed since the 'It source was turned on, the q9 output of the binary counter 1B becomes H level1), R8
Since the 7 liters 70 knob 28 is set, the Q output goes to L level and ASWON also goes to L level as shown in FIG. As a result, the output of the AND gate 69 is at L level, NAR
The output of the D gate 6B becomes H level, the constant current sources C and θ stop operating, and the above-described charging and discharging of the capacitor 48 is stopped. Therefore, the charging potential of the capacitor 48 at this point in time is latched, and a current equivalent to the voltage latched in the capacitor 48 flows constantly through the current mirror f.

At this time, the output Q of the R87 lip-flop 28 is inverted to the L level as described above, so the output 1R of the AND gate 205 is
OFF1 also changes from H level to L level as shown in FIG. Also R
Since the output of the e-flip-flop 31 has also been initially reset as described above, 1ROPF 2 is also held at L level. Furthermore, as mentioned above, the output Q (AFET) of the Re flip-flop p-tube 97 is at the L level at the initial reset.
Since the Q output 0PEN of the S flip-flop 20 is also held at the L level, the A11D gate 207 is at the L level.As a result, when the output Q9 of the counter 18 shifts to the H level, the OR gate 118 The output of the AF shifts from H level to L level, and the transistor 115 turns off.
Since the ST signal is at L level, this resistor 113,1
14, the transistor 112 is open, and the resistor 111.1-
All the current of the constant current source g formed by the transistors 109 and 110 flows to the base of the transistor 106. The capacitor 108 is charged by the current from the emitter output of the transistor 106 via the resistor 107, and its terminal voltage is applied to the voltage of the OP amplifier 105.

Therefore, the 1RED 105 is gradually biased to a high level as shown in FIG. 5 according to its voltage value. Here resistance 1
04 adjusts its bias state, and transistor 102 supplies current to 1RKD. Further, the signal of 1ROIJ, which is an inverted signal of the output pulse from the output terminal of the Johnson counter a, is applied to the transistor 119 via resistors 120 and 121, and is further applied to the transistor 119.
Since the collector of 19 is connected to the OP Ang 1050 stroke terminal, when 1RON is at H level, O
The output of the P amplifier 105 is zero, that is, 1RFtD is not lit, and when lROM is at L level, iRFiD is lit. Therefore, 1RED gradually increases its output while lighting up at a constant cycle in synchronization with the output pulse of Johnson counter a. This 1RED
When the reflected light from the object illuminated by the lighting of the PSD 45 enters the PSD 45 via the light receiving optical system, a signal current is generated, which is converted into a voltage through the feedback system 46. The signal voltage is applied to an OP amplifier 75 via a capacitor 71, and is amplified to an appropriate value by the values of resistors 73 and 74.

Also, at this time, the RS flip-flop 26 is the counter 18.
Since the flip-flop 26 outputs the H level from Q, the result is A.
ND game) 32.53 output 8PId, 5PL2 is NAND according to the set state of Johnson counter a
Game) 16.17 is determined by the output, and as shown in FIG. 4, when the signal lROM is at L level, that is, when 1RKD is lit, 5pL1 goes low at a predetermined timing.
level, and lROM is at H level, that is: LRIl
When iD is not lit, SPL 2 indicates L level at a predetermined timing.

Analog switch ASW 76.77 transmits input to output in response to L level, so iRF! The output of the OP amplifier 75 when D is lit is sampled and held in a capacitor 79, and the output of the OP amplifier 75 when it is not lit is sampled and held in a capacitor 82. The output of the OP amplifier 75 held in the capacitor 82 is inverted by the inverting amplifier 87iC via the buffer amplifier 83.

The output of the inverting amplifier 87 and the voltage held in the capacitor 79 outputted via the buffer amplifier 80 are input to an adder circuit composed of resistors 88, 89, 90, 92 and an OF amplifier 91, and are added together. This is J) PS
A signal output corresponding only to the reflected light from the 1RFfD incident on D can be obtained, and the offset of the op amp 75 can be canceled.

The output of this adder circuit is input to the negative terminal of the next-stage comparator 94, and the input of the positive terminal of this comparator is set by a variable resistor 93 to a constant value that is higher than the negative terminal level when the power is turned on. There is. Since the output of the adder circuit is inverted, the output of the adder circuit gradually increases as the output of 1RED increases, and when the plus input reference level of the comparator 94 becomes higher, the output of the comparator 94 becomes L level. Become. As a result, the BS that was reset by the pvc signal
Since the L level is input to the S terminal of the flip-flop 97, this flip-flop is set and AFST changes to the ■ level.

AFSTB K Ha:I depending on API3T R level
A differential waveform according to the time constants of the processor 98 and the resistor 99 is output, and this output is further applied to the reset input of the binary counter 18 via the OR gate 15 to return the counter to its initial state. At the same time, AFST has a resistance of 115,1
14 to the transistor 112 and outputs it to O.
By stopping the constant current source g (D), charging of the capacitor 108 is stopped. From this, it is possible to maintain the output of 1RED at a constant value when the signal output reaches a constant level. That is, by this operation, the IA described in FIG.

Further, since the counter 18 restarts the counting operation after being set again, the counter 18 outputs an H level from the output Q6 after a certain period of time has passed after being set again. Also, at this time, as mentioned above (AF8T has 5 levels, NAND
Gate 19 outputs L level in response to Q6 (■ level), and RS flip-flop 20 is set. Therefore, the 0PFtN signal changes to H level. When the 0PEN signal is input to transistor 110 via inverter 57 and resistors 58 and 59, this transistor is turned off, so the current from the constant current source flows to transistor 41 and this transistor is turned on. This is j5 PSD
The output current has a value depending on the subject distance. That is, 1R
The PSD 45 as a light-receiving element is arranged so that the light reflected from the subject by the light projection of the 1RFliD is received by the PSD 45 as a light-receiving element via a light-receiving lens arranged at a base line distance from the light projection axis of the ED 103. Therefore, the light receiving point on the PAD corresponds to the subject distance as described in FIG.

Also, since the transistor 41 is on as described above, the terminal A of the PSD at this time is
The output current Em from is according to the above light receiving point, that is,
The value depends on the subject distance.

At this time, the current flowing through the current 7-f corresponds to the DC component included in the output of the PAD when the transistor 41 is off in the above-described operation. Therefore, in order to remove the DC component included in the output of the PAD when the transistor 41 is on, it is necessary to reset the value of the current flowing through the current mirror f.

Therefore, it is AN that the above 0PFiN has become H level.
It is detected by the D gate 34, and the H level is transmitted to the AND gate 202, causing the ASWON to shift to the H level again as shown in FIG.
By making it respond to OH, the above-mentioned capacitor 48
The charging and discharging operations are performed to control the current flowing through the current mirror f and the output current of the light receiving element 45 to be equal to each other.

On the other hand, the counter 18 performs a counting operation after being set again, and after a predetermined period of time, the output QB is brought to the ■ level, whereby the j5 NAND gate 22 sends out the L level and resets the flip-flop 27. For this reason, A
The ND gate 64 outputs L level, and the AND gate 20
The output Aswoa of No. 2 also becomes L level again, and charging and discharging of the capacitor 48 is stopped as described above, and the current of the current mirror f at this time is held from now on, and the current flowing through the current mirror f becomes the current of the light receiving element. The current value is maintained to be equal to the output current value, and the current flowing through the current mirror f is reset.The output of the POD when the transistor 41 is on is passed through the current mirror f, and the saturation of the first stage amplifier in this case is also avoided. It is prevented.

On the other hand, at this time, the lighting level of 1RFiD is lit at a certain lighting level when the voltage corresponding to M+ is set to a certain level, so based on the light receiving element output M at this time The output accurately corresponds to the object distance, and the signal output from the adder circuit 91 in the above operation also shows a value corresponding to the object distance.

After that, when the count of the counter 18 progresses and Q7 becomes H level, the NAND gate 24 outputs L level and Q7
Reset the lipfrog 29. Since 7 lip-flop 30 is set, AND gate 3
6 outputs level ■ in response to the reset of 29. Furthermore, since DOWN above indicates the fifth level, HAND
The gate 204 outputs the JL level based on the R level of the gate 36, and furthermore, at the L level, the NAND gate 210 outputs the V level.
Set AON to R level.

Therefore, the analog switch 95 responds to VAON, the output of the adder circuit 90 is collected by the capacitor 100, and the output Vm corresponding to the above M is output from the buffer amplifier 10.
1, and the amplifier 101 outputs an output ■A corresponding to the subject distance.

As described above, in the present invention, when the output from the PsD is a large current, current is caused to flow through the current mirror f to prevent the first stage amplifier from being saturated, and even when the output from the PEID is a large current, the current can be accurately maintained. It is possible to obtain accurate distance information.

Next, a case where the brightness level of external light is low will be explained using FIG. 5.

In this case, in addition to turning on the power and detecting the output level of the light receiving element as described above, the output of the light receiving element 45 (from M10)
Since is a relatively small current, the output of the OF amplifier 47 becomes higher than the set level α (latch down level) of one input terminal of the comparator 200. Therefore, the comparator 200 does not send out the L level and is held at the ■ level, and as a result, the output DOWN of the flip-flop 201 is held at the L level. Therefore, the output ASWO of AND gate 202
When N is at L level, charging and discharging operations of the capacitor 48 are prohibited. Also, since the DOWN output is at L level,
1ROFF 1 is also L level, and even 1ROFF
Since 2 and 1ROFF 3 are initially at the L level as in the above-described operation, the transistor 115 is gradually turned off after the power is turned on. For this reason, 1RED10
5 also lights up immediately and gradually increases the lighting level. Thereafter, in the operation described above, the output level of the light receiving element increases in accordance with the increase in the lighting level of 11D, and when it reaches the above-mentioned certain level, the comparator 94 is inverted and AFST becomes H level. The level is held constant, and then the transistor 41 is turned on by the operation described above, the signal current is sent out from the light receiving element, and the voltage A as distance information corresponding to the signal current is transmitted as described above. It is sent from the buffer amplifier 101. Even in the signal current detection operation, since DOWN is held at the L level, ASWON also continues to be held at the L level, and the :t;i- current operation to the capacitor 48 is performed. Therefore, when the brightness level is low and there is no risk of saturation of the first stage amplifier with the output of the light receiving element, the current suppression operation is not performed and the detection operation of the signal current Em is immediately executed. Operation time is reduced and distance measurement is performed quickly.

In the above embodiment, a processing circuit is used only on one side of the PSD for signal processing, but the present invention is also applicable to cases where processing circuits are used on both sides of the PSD, and two light receiving elements or a plurality of light receiving elements are used. It goes without saying that the present invention can also be applied to distance measuring devices using elements.

In addition, the DC suppression control comparator 52 and the luminance level/l''
It is possible to use the l'[l constant comparator 200 and c) by setting the comparison level to an appropriate value.

As described above in detail based on the embodiments, according to the present invention, when the brightness level of outside light is high and the first-stage amplifier reaches saturation or reaches K near it, DC light is removed only to reduce the brightness level. If it is low and does not affect distance measurement, the DC light will not be canceled and the distance measurement operation will immediately start.
The time required for direct current suppression is shortened, and rapid distance measurement becomes possible.

[Brief explanation of drawings]

FIG. 1 is a sectional view of a PSD as a light receiving element used in a distance measuring device according to the present invention, FIG. 2 is a circuit diagram showing an embodiment of the distance measuring device according to the present invention, The figure is a waveform diagram for explaining the operation of the second illustrated embodiment. +1. f... Current mirror circuit e, a... Constant current source 47... Operational amplifier 200... Comparator patent applicant Canon Corporation

Claims (1)

[Claims] A light projecting element that projects pulse-modulated signal light toward a subject; a light receiving element that receives reflected light from the subject due to the light projecting operation of the light projecting element; and a distance to the subject is detected based on the output of the light receiving element. a processing circuit, a detection circuit that detects a DC signal level included in the light receiving element output; and a DC signal suppression that removes the DC signal level detected by the detection circuit from the light receiving element output. and a discrimination circuit for activating the DC signal suppression circuit only when the DC signal level detected by the detection circuit is larger than a predetermined value. .