JPS6033590A - Video address controller - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical field to which the invention pertains] The present invention relates to a video address control device for controlling addresses for display and storage sent to a video memory in a video display system.

[Prior art]

In a video display system that uses a raster scan type CRT as a display device, when data to be displayed is stored in a large capacity video memory (this operation is hereinafter referred to as "drawing"), an address for the end of the drawing is supplied, When reading data from the video memory and displaying it, a display address is supplied. It is well known that by sequentially changing this display address, different display data is read out from the video memory and a video serial signal is obtained. Conventional video address control devices that read display data from a video memory can be broadly classified into two types as described below.

FIG. 1 is a block diagram showing essential parts of an example of a conventional video display system including a video memory address generator as a video address control device. The number of dots displayed on the screen is 256
For example, if we take a graphic display that has a video memory configuration of The number of addresses required for display in one scanning line period is 16 addresses, expressed as 256/16. Furthermore, when a display period section of 256 scanning lines is taken in the vertical direction of the screen, the video memory is 16×256. That is, a memory having a capacity of 4096 addresses/16 bits is required. This capacity is the same in the case of the second conventional IT described later.

The video memory address generator l is an incrementer with a sufficient number of bits (12 bits) to address the above 4096 addresses, and the contents are changed by 11'' every unit time (16 bit display time in this conventional example). Furthermore, at the end of one screen display, its contents are cleared to @0'' and the next screen is displayed as a prefix (#). This video memory address signal is sent to the central processing unit (CPU) (Fig. (not shown) is input via the video memory address bus 6 to an address bus switch 2 to which an address signal is supplied from the CPU # via the address bus 8. When the state of the address switching signal 14 generated when writing or reading data to or from the video memory 3 is inactive, the address of the video memory 3 is connected to the address of the video memory 3 via the video memory address bus 7. , a 16-bit output is outputted to the video memory data bus 10 according to the address signal, and the parallel -
In this case, a video serial signal 16 is obtained via a serial converter 5. In FIG. 1, 4 is a data bus switching driver for separating the CPU data bus 11 and the video memory data bus 10, and 15 is a data bus switching signal. Furthermore, 9 is a CPUφ memory control bus, 12
is a clock signal generator (not shown) when the screen exits
13 is a display erase signal from the clock signal generator indicating that the display period is out.

FIG. 2 shows the timing of various signals supplied to the video memory l address generator 1 and the generated address signals. The video memory address generator 1 is cleared to 10'' by the screen end signal 12 generated at the end of the screen, and when the display erase signal 13 indicating that it is outside the display period is ``H'''', the video memory address signal is cleared to 10''. It does not occur and its value does not change.When the display erase signal becomes ``L'' and display starts, the video memory address signal is generated only once during the 16-bit display period K, and the video memory l address is @1''.
and read different data.

FIG. 3 is a block diagram showing essential parts of an example of a conventional video display system using another video address control device. In this conventional example, DMA (DirectMemory
This device is equipped with a CRT controller 18 having two lines of line buffers, a DMA request line, etc. as a video address control device, and the address of the video memory at the start of screen display is DMA.
The DMA request signal 22 is reset to the controller 17 under the control of the CPU every time the screen display ends.
The data is output from the CRT controller 18 to the DMA controller 17 only for the period necessary for DMA transfer of the address necessary for displaying one line. DMA controller 17 is DM
After receiving the A request signal 22, the CPU is stopped and the address bus, data bus, and control bus are released (C
A occupancy request signal 20 is sent to the PU. CPU
When the quick approval signal 19 is input to the DMA controller 17, the DMA controller 17 starts DMA transfer and sends the DM to the CRT controller 18.
A DMA approval signal 21 indicating that A transfer is being executed is sent. Upon receiving the signal, the CRT controller 18 determines whether or not there will be a subsequent DMA transfer, and sends the DMA request signal 2.
Perform the second control.

DMA request request signal 2 0 The DMA controller 17 is activated according to the procedure described above, and the DMA
A video memory address signal is applied from the A controller 17 via the CPU address bus 8, and a memory control signal is applied via the CPU memory control bus 9 to the image memory 3, and data output corresponding to the address is provided. The signal is sent to the CRT controller 18 and stored in the first line buffer prepared for displaying the next line. Data currently being displayed is stored in the second line buffer, and is sent to the parallel-to-serial converter 5 to obtain a serial video signal 16 according to the display timing.

FIG. 4 shows a DMA request signal 22 and a DMA controller 17.
This shows the timing of addresses and display data generated by. When the screen end signal indicating the end of the screen becomes active, the DMA controller 17 receives the display start address @0''.
is set and the DMA request signal 22 is sent from the CRT controller 18, the address "IO" of the video memory 3 is set.
15" is transferred to the first line buffer built in the CRT controller 18. With the start of display, the contents of the first line buffer are sent to the parallel-to-serial converter 5. Displayed on the CRT
The DMA request signal 22 is output from the controller 18.
Data from video memory addresses "16" to "31" where display data for the next line is stored is transferred to the second line buffer.

In general, the displayed content is often viewed from the front of the display screen, and if the screen is not split or complicated winding operations are performed, it is possible to achieve the desired result even with only sequential address changes as in the conventional example above. is obtained. However, depending on the application, the screen may be viewed from above or below, or the screen may be viewed by reflecting it on a mirror or the like. When viewed from above, the image appears upside down, and the image reflected in the mirror has the upper and lower cloths reversed, that is, the image is turned upside down.

With the above-mentioned conventional device, which can only increment the display address and read out data that has not been stored in the next consecutive address, it is impossible to correct such a display to make it a normal display screen. There is a problem.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a video address control device that can easily realize a vertically and horizontally inverted video display by solving the above-mentioned problems, and has a highly flexible display control function with a large degree of freedom. It is in.

[Structure of the invention]

The video address control device of the present invention is a video address control device for a video display system that sequentially changes the address of a video memory that stores video data and displays the read data on a display device. a count register whose contents are cleared for each unit character or solid display section; a pitch register that stores the entire number of addresses in the display progress direction of the video memory; and a flag register that sets an address calculation method.

It is constructed by including address calculation control means for performing predetermined address calculation and control based on the settings of the flag register.

[Explanation of Examples]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 5 is a block diagram showing essential parts of an embodiment of the present invention.

91 This embodiment includes a display address register (DAD) 23 that stores a display address, and a count register (CHR) 24 whose contents are cleared for each character or figure display section.
, a pitch register (PITCH) 25 that stores the number of addresses in the display progression direction of the video memory, a flag register (FLAG) 26 that sets the address calculation method, and a predetermined address calculation based on the settings of the flag register 26. It is constructed to include an arithmetic unit 27 and a buffer register (DAD') 28 as address arithmetic control means.

This embodiment corresponds to the video memory address generator 1 in FIG. 1 showing a conventional video display system, and the video memory address generator 1 is a mere incrementer. Register, DAD23. C8H17,
PITCH25, FLAG26. The difference is that it is composed of a DAD' 28 and an arithmetic unit 27.

The DAD 23 is not used for address calculation, and new address data is set by the CPU 10- at the start of one-screen display. CHR24 operates as an incrementer and outputs a control signal "'Ct(R+l→CHR"(CH
R+1 → CHR adds 1 to the data in CHR and converts it to CHH
This means that it is stored in . Similar expressions below are also expressed in the same way. ), the operator 2
7 to achieve its function. Each time one line of display ends, the value is cleared to 10'' by control signal 04CHR (clear to CHR data t-0). PITCH 25 stores the number of addresses of the video memory in the display scanning direction, It can be set to any value in advance by the CPU.1) AD' 28 is a register that temporarily stores the result of address operation, and this output is output via the video memory address bus 6. for,
Connected to the video memory address. FLAG 26 is a register for changing the address calculation method in arithmetic unit 27, and can be set to any value by CPLI.

In this embodiment, the flag consists of 2 bits, and by changing the value, the first
As shown in Figure 0 (a) and (b), one of the following four types of address performance methods is selected.

■DAD+CHRDADI DAD+PITCH-1→DAD, DAD/■DAD-
CHRDAD' DAD+PITCH-1→DAD, DAD/■DAD+
CHRDAD/ DAD-PITCH--→DAD, DAC'■DAD-
CHRDAD' DAD-PITCH-1→DAD, DAD' In each of the above calculation methods, the calculations in the upper row are not performed during the display period, and the calculations in the lower row are performed every time the line display starts. The timing relationship of address calculations is shown in FIG. However, regarding the change in display address, only the above case (■) is shown.

The operation of one embodiment of the present invention will be explained below with reference to FIGS. 5 and 6.
This will be explained using figures.

When the screen end signal that is generated every time one screen ends becomes active, the display start address on the DAD 23 becomes the main control of the CPU.
It is set during the period when the display address setting signal from the CPU is 'H', and the CHR24 is cleared to '0'. To DAD23, in the case of FIG.
In the figure, ``P-1'' (P represents the setting value of the PITCH register, in this example, P = 28.), and in Figure 9, 1(N-1)P'' (N is an integer value, in this example, In the example, N=10
゜) In Fig. 10, NP-1'' is set by the CPU before starting single-screen display.

During the display period, each address cycle of the video memory
After the CHR24 is incremented by 1'', the value is maintained between the CHR24 and the DAD23, which continues to hold the same value during the 1-line display period.
Addition and subtraction are performed according to the set value of FLAG 26, and after the result is temporarily stored in DAD/28, it is supplied to the address of the video memory. When one line finishes displaying,
FLAG26 between DAD23 and PITCH25
Addition and subtraction are performed according to the set values of hl and the result 13- is stored in DAD 23 and DAD' 28 to prepare for displaying the next line and subsequent lines. The above-described calculation cycle is repeated to form one screen display.

Figure 7 (a), (b) fi to Figure 10 (a), (
b) is obtained from the results of this example, and the map of the ii display address is shown in each figure (a) as the display figure (here, the Roman letter "F").
is displayed. ) are shown in each figure (b).

In the case of FLAG "00" shown in Fig. 7 (a) and (b), 1 In the normal case, the FLAG shown in Fig. 9 (a) and (b)
In the case of G"'10", the FL shown in FIG.
In the case of AG "01", the FLA shown in Figures 7 (a) and (b)e is shown in Figures 10 (aJ and (b) when horizontally reversed).
The case of G"tl" corresponds to the case where FIGS. 9(a) and (b) are reversed left and right.

That is, according to this embodiment, four types of display can be performed by setting the calculation method using FLAG.

In the above embodiment, the flag of the flag register is 2 bits, but the flag is not limited to this, and by increasing the number of bits, 14- can be displayed in many ways.

〔Effect of the invention〕

As described above in detail, the video address control device of the present invention includes a display address register that stores display addresses, a count register whose contents are cleared for each unit of text or graphic display section, and a video memory. includes a pitch register for storing the number of addresses in the display progress direction, a flag register for setting an address calculation method, and an address calculation control means for performing predetermined address calculation and control based on the settings of the flag register. Therefore, it is possible to easily realize a vertically and horizontally inverted video display, which was previously impossible, and it has the effect of providing a highly flexible display control function with a large degree of freedom.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing the main parts of an example of a conventional video display system, Fig. 2 is a timing diagram for explaining the operation of the system shown in Fig. 1, and Fig. 3 is a block diagram of another conventional video display system. A block diagram showing the main parts of an example, Fig. 4 is fAc3
5 is a block diagram illustrating an embodiment of the present invention; FIG. 6 is a rounded timing diagram illustrating the operation of this embodiment; and FIG.
at, (b) to FIGS. 10 (a) and (b) show changes in the display address according to the flag register settings in this embodiment [q! r diagram (a)] and the displayed figure at that time [
FIG. 1...Video memory address generator, 2...
...Address bus cutter, 3...Video memory,
4... Data bus switching driver, 5...
・Parallel-serial converter, 6.7...Video memory address bus, 8...CPU address bus, 9.
...CPU memory control bus, 10...Video memory data bus, 11...CPU data bus, 12...Screen end signal, 13...・
Display erase signal, ]4...Address clear signal, 1
5.・. ...Data bus switching wandering number, 16...Video IM
Column signal, 17...l) MA controller, 18
...CRT=r controller, 19...
Hold approval signal, 20...Hold request signal, 21...DMA approval signal, 22...
DMA request signal, 23...Display address register (DAD), 24...Count register (C
HR), 25...Pitch register (PITCH
), 26...Flag register (FLAG), 2
7... Arithmetic unit, 28... Buffer register (DAD/). 17- +2 figure

Claims (1)

[Claims] In a video address control device of a video display system that sequentially changes the address of a video memory that stores video data and displays the read data on a display, there is a display address register that stores a display address, and a 1-unit character or graphic display. A count register whose contents are cleared for each section, a pitch register that stores the number of addresses in the display progress direction of the video memory, a flag register that sets the address calculation method, and a predetermined register that stores the number of addresses in the display progress direction of the video memory. A video address control device comprising address calculation control means for performing address calculation and control.