JPS6036618B2 - information processing system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an information processing system, and more specifically, the present invention relates to an information processing system having a buffer memory control means for preventing the occurrence of logical contradictions due to content mismatch between a buffer memory and a main memory. Regarding the system.

In information processing systems, there is a large gap between the speed of a central processing unit (hereinafter referred to as a processor) and the speed of a main memory, and this is a factor that limits the performance of computer systems.

To alleviate this problem, there is a buffer memory method in which a relatively small capacity buffer memory is provided on the processor side.

In this method, when accessing main memory from the processor, a block consisting of multiple words including the word to be accessed is captured in a buffer memo, and the next time the access is made, this buffer is accessed. It is known that by doing so, it is possible to effectively speed up the main memory. The buffer memory method has been adopted in many computer systems, especially a set in which main memory and buffer memory are divided into multiple sets, and only blocks belonging to the same set are allocated from main memory to buffer memory. Associative method [C. J. Conti “The concept of buffer storage”
toge”Computer Group.News
) Buffer memory is commonly used. However, in a buffer memory system, as mentioned above, a buffer memory is provided for each processor, so for example, when writing data from an input/output device to main memory, the data is written only to the main memory. .

At this time, if the main memory area containing the data has already been loaded into the buffer memory, a content mismatch will occur between the buffer memory and the main memory. In order to prevent this, conventional methods have been used in which newly updated information is fetched from main memory by erasing the entire buffer memory every time the processor switches the process to be executed or every time there is an input/output interrupt. '1}, or each time there is a write request from the input/output device to the main memory, the address is sent to the buffer memory, it is searched to see if this address exists on the buffer memory, and if it is, the address is sent to the buffer memory. A method {2) is used in which content mismatch is prevented by erasing corresponding blocks. This method ■
has multiple computer systems. . It is also used in multiprocessor systems with processors. That is,
In a multiprocessor system, if a process P that was being executed on a certain processor A at a certain point in time is executed on another processor B, and writes to a certain address in main memory, the process P that was executed previously will be Processor A's buffer memo is retained, so the contents of that address are not updated, so process P
When executed by processor A, old content on the buffer memory that is different from the main memory is read, which may lead to unintended processing. In order to prevent such inconveniences, when writing to main memory, the address is sent to another processor, thereby erasing the corresponding contents of the buffer memory of the other processor. However, if a method such as method 1) of erasing all the contents of the buffer memory is used, the contents of the buffer memory will be erased frequently, and the probability that the necessary information will be found in the buffer memory (hit rate) will decrease. This has the drawback that the effective access time is not significantly improved.

In addition, method (2) in which the write address to main memory is also sent to other processors has the disadvantage that access from the original processor is delayed due to the search for the write address from other processors or input/output devices. . Further, a signal path for sending a write address from one processor to another processor, and an access control mechanism for controlling access from other processors to the buffer memory and access from the original processor are required. When the number of processors is large, the amount of hardware for these becomes enormous, and other functions are required. Since the number of accesses from the o setter also increases, the performance of the buffer memory is significantly degraded. In this system, in order to reduce the frequency of write address searches, each processor has an address array that holds the blocks currently stored in the buffer memory of other processors, and when a write operation is performed, this address is There are also known methods that reduce the number of searches in the buffers of other processors by searching the array, but these methods also require the aforementioned signal path for the write address to the other processor, The problem of the amount of hardware for access control mechanisms etc. cannot be solved.

In addition, in method (2), since the hardware configuration differs more than the number of processors, it is necessary to consider how to connect the maximum number of processors. There was a drawback that it had to be done.

Therefore, a method is required to erase only the necessary portion of the buffer memory at the time when a logical contradiction occurs, such as by dispatching the buffer memory or starting an input operation. When trying to perform such processing, in the conventional method, it is necessary to search the management table for all sets for each erase and check whether the block in each set is the corresponding block to be erased. It requires a lot of time and is not realistic.

The present invention aims to eliminate these drawbacks, and the purpose of the present invention is to maintain the content between buffer memory and main memory without increasing the amount of hardware or degrading performance even when the number of processors increases. The objective is to provide an information processing system that can resolve discrepancies.

Another object of the present invention is to provide a means for quickly erasing only the portion related to the occurrence of content mismatch between the buffer memory and the main memory.

In the present invention, when accessing data belonging to an information unit that may be written, the identification number of the information unit and the current address tag of the information unit are added to the address of this data, and these are added to the block buffer. Registration to memory and search are performed.

By changing this address tag at the time when there is a possibility that there will be a content mismatch between the main memory and the buffer memory, the corresponding data is equivalently erased from the buffer memory. Furthermore, for information units that are clearly not to be written, that is, read-only information units, the address tag part is ignored when accessing them, so that they are not erased from the buffer memory even when the address tag is updated. By this,
It is possible to erase from the buffer memory only data whose contents are changed by writing.

As a result, in a set-associative type buffer memory, only necessary information units can be erased from the buffer memory at high speed without searching the entire set.

Furthermore, according to the present invention, the amount of hardware is increased by an identification number of an information unit, a data path for application, retention, comparison, etc. of an address tag, a management table, a comparison circuit, etc. related to the tag attached to the address. It's just something.

Therefore, even if the number of processors increases, the same hardware configuration and control method can be used, and the performance does not deteriorate. Furthermore, the present invention is also applicable to a multiprocessor system having a plurality of processors that includes a processor that does not have a buffer memory. The present invention will be explained below with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of an information processing system according to the present invention.

In this embodiment, it is assumed that the buffer memory is accessed using real addresses.

Furthermore, it is assumed that the information unit for erasing the buffer memory is a process, and furthermore, in the information processing system in this embodiment, the storage location where instructions are stored and the storage location where operands are stored are separated and the same. It is assumed that it is guaranteed at the time of program creation that the program is not stored in the block , and that a method is adopted in which the contents of the program section are not changed.

This method of distinguishing between the program section and the operand section is often used in recent information processing systems. In this embodiment, it is assumed that the operand portion of each process is erased from the buffer memory for each process. In this embodiment, whether the access to the buffer memory is an instruction fletch or an access to an operand is applied to the buffer memory as an access factor for each memory access, and by determining this, the information to be accessed is It is assumed that it is possible to determine whether or not the image is for use only for displaying.

In this embodiment, since a process is used as the unit of information to be erased, a discrepancy in content between the buffer memory and the main memory may occur if a process is executed on a processor and then executed on another processor. The time when a process enters the waiting state by issuing an input command from an input device is detected, and the address tag held for each process is counted up at these times. As a result, only the operand part of the contents of the buffer memory used by the process before the update becomes inaccessible, and has the same effect as if it had been erased.

Therefore, in this embodiment, the management table for managing the blocks currently stored in the buffer memory includes not only the main memory address as the block address, but also the process number, which is the unit of information for erasure, the address tag of the process, and its address tag. A field is provided that holds a write bit indicating whether the block is the one that is being written to.

These fields are used when searching, and when accessing, access factor information indicating whether the access is to an operand or issuing a command is also applied to the buffer memo. Also, each program executed on an information processing system.

Each process has a process control block to hold the current instruction address, condition code, each register, etc. However, in this embodiment, in order to manage the buffer memory, the control block contains information about the process in addition to these information. The processor number on which the process ran and the current address tag value for that process are also maintained. The processor number is used to detect the trigger for erasing the buffer memory. It is assumed that the process control block is stored on the main memory. In this embodiment, as described above, the process number, address tag, and access factor are sent from the processor address register of the processor 7 to the buffer memory 8 along with the main memory address, and applied to the address register 2.
The process number address tag is the first in address register 2.
and the second fields 21 and 22, respectively, and the block address section, set address section 14, and word address section 15 from the upper part of the main memory address are applied to the third, fourth, and fifth fields 23 of the address register 2, respectively.
, 24 and 25, respectively. Furthermore, the 1-bit access factor is stored in the sixth field 26 of address register 2.
is stored in

The buffer memory is implemented using a set associative method, and the buffer memory is configured so that each set can hold two blocks belonging to the same set on the main memory. Therefore, the management table 3 for managing the main memory blocks currently held in the buffer memory has an entry corresponding to each set, and each entry corresponds to the first and second blocks in each set. It has 2 fields.

The first and second fields further include first and second process number parts 311, 321 having process numbers, first and second address tag parts 312, 322 holding address tags, and a second process number part 312, 322 holding block addresses. 1
and second block address sections 313, 323, each block. Each block has first and second valid bits 314, 324 indicating whether the blocks are currently available in the buffer memory and write information bits 315, 325 indicating whether each block is a block to be written to. Process number section 3 of first and second fields of management table 3
11, 321, address tag sections 312, 322, and block address sections 313, 323 are the first and second values, respectively.
It is applied to one input of the process number comparison circuits 511, 521, 1, the first and second address tag comparison circuits 512, 522, and the first and second block address comparison circuits 513, 523. Other inputs include the first, second and third fields 21 of address register 2.
, 22, and 23 are applied, respectively. Note that these values are also applied to the first and second fields 311 and 321 of the management table 3 as write data to the management table 3. The buffer memory array 4 also stores the values of the block address section 23 and set address section 24 of the main memory address and the block address section 24 from the control circuit 6.
A block address 61 is applied as an address, and data can be transferred between the main memory 9 and the processor in response to a command from a control signal line 63 from a control circuit. Also, the write bit 26 of the sixth field of address register 2 and the first and second bits of the management table
The values read from the write bits 315 and 325 are applied to the control section 6 (not shown).

Next, the operation of this embodiment will be explained.

First, when a certain process is dispatched to a certain processor, the processor reads the processor number section indicating the processor number on which the process was previously executed from the process control block (not shown) in main memory, and compares this with the current processor number. Compare the processor numbers of .

If this is different from the current processor number, the new processor number is returned to the process control block, the processor number is updated, an address tag is sent from the process control block, this is counted up and updated, and the processor number, address tag is stored in the first and second fields 11, 12 of the processor address register 1. If the processor numbers are the same, the process number and the read address tag are stored in the processor address register 1 without updating them.

When the address tag is counted up, if the address tag does not overflow, actual processing for that process is started during the above-described operations. If the address tag value overflows when counting up, it is guaranteed that there are no blocks remaining in the buffer memory that have the same previous tag value, belong to the process, and may be written to. In order to do this, an erase signal is sent to the buffer memory 8 along with the process number via the signal line 71, and the buffer memory starts erasing all blocks belonging to that process and to which there is a possibility of writing.

After the erase completion signal is returned from the buffer memory 8 via the signal line 65, processing for that process is started.
Regarding memory access from the processor when executing a process, the third
, fourth, and fifth fields 13, 14, and 15, and an access request is applied to the buffer memory 8 via a signal line 71 together with an access factor. When this access request is received, the following operations are performed under the control of the buffer memory control circuit 6.

That is, first, the address and access factor sent from the processor 7 are stored in the address register 2, the management table 3 is read out using the value of the set address section 24 as an address, and the first, second and third 311, 312, 313 Comparison circuits 511, 512, 513, 521, 522
, 523, when a match is detected in the first field compared with the value of each corresponding field of the address register 2, that is, when the corresponding valid bit extracted from the management table 3 is 1 and the value of the corresponding field of the address register 2 is detected. When the write bit of the sixth field 26 is 1 and the first process number comparison circuit 511, address tag comparison circuit 512, and block address comparison circuit 513 all output a coincidence detection signal, or the sixth field of the address register 2
field is 0 and the first process number comparison circuit 511 and block address comparison circuit 513 output a coincidence detection signal, the first
The requested information is stored in the block, and the buffer memory array 4 is accessed via the signal line 63. Similarly, if a match is detected in the second field, the second block of the corresponding set of buffer memory array 4 is accessed. The control circuit 6 specifies the first and second blocks.
It is designated by the block address line 61 output from the block address line 61.

There are two cases in which no match is found in either the first or second field. That is, when the write bit 26 of the address register 2 is 1, if there is a mismatch in either the first and second process number comparison circuits 511, 512, address tag comparison circuits 512, 522, or block address comparison circuits 513, 523. This is the case when the write bit is 0 and a mismatch is detected in either the first and second process number comparison circuits 511, 521 or the block address comparison circuits 513, 523.

At this time, the requested block is not stored in the buffer memory array 4, and it is necessary to allocate a buffer memory to the block. First, select one of the first and second blocks of the buffer memory, and request the process number section, address tag section, block address section, and write bit of the selected first and second fields of the management table. Write the value corresponding to the address where it was and set the valid bit to 0. At the same time, a block transfer request is issued to the main memory via the signal line 64. After the transfer is completed, the corresponding valid bit in the management table 3 is rewritten to 1, and the buffer memory is accessed. Further, when a buffer memory erase signal is applied from the processor via the signal line 71 along with a process number, the following operation is performed under the control of the control circuit 6.

That is, first, 1. The process number is stored in the first field 21 of the address register 2, and the value of the set address counter 62 provided in the control circuit 6 is reset.

2 Next, the management table 3 is set based on the value of the set address counter 62, and the first and second process number comparison circuits 511 and 521 compare the process number read from the management table with the process number in the address register 2. compare.

When the corresponding block is a block to which writing is performed, that is, when the write bit read from the management table 3 is 1, the corresponding comparison circuit 511 or 521
If a match is detected, the corresponding valid bit is reset to 0 and written back to the management table.

If the write bit is 0, there is no need to erase it, so
The valid bit is not reset. 3 After counting up the set address counter 62, perform the operation 2.

4 After performing operations 2 and 3 until the set address counter overflows, the signal line 6 is connected to the processor 7.
5 to send an erase completion signal.

By the above operations 1 to 4, erasing has been performed for the blocks of the buffer memory used in the designated process, except for the data whose contents have been changed by writing.

Next, a second embodiment of the present invention will be described with reference to FIGS. 1 and 2.

In this embodiment, it is assumed that the information processing system employs a segmentation-based virtual memory in which a segment, which is a logical unit of a program, is the unit of allocation to the main memory, and the buffer memory also has real main memory addresses. It is assumed that virtual addresses are used instead of virtual addresses.

It is also assumed that erasing of the buffer memory is performed in units of segments, and that only segments to which writing is performed are erased as necessary.

Note that FIG. 2 shows a block diagram of the processor 7 in this embodiment. To achieve this, in this embodiment, an address tag and the last processor number to which the segment was accessed are managed for each segment.

These are placed in segment descriptors on main memory. In this embodiment, the memory address A is represented by a designated number RN and an intra-segment displacement D of a segment descriptor register SDR provided in the processor 7, as shown in FIG.

Each entry in the segment descriptor register SDR has a segment address and a corresponding address tag.

In an information processing system with such a configuration, when a certain process is dispatched to a certain processor, the segment that can be used by that process is checked, and after checking that it is a valid segment, the address A and main address of this segment are checked. Write information W indicating whether writing is permitted for the segment read from the segment descriptor on storage, segment length SL, etc. are stored in the corresponding segment descriptor register SDR.

Once the segments that can be used by a certain process have been registered in the segment descriptor register SDR, actual processing of the process begins. Therefore, in this example,
When checking the segment to be erased from the buffer memory during dispatch, the processor number in the segment descriptor is compared with the current processor number, and if they are equal, it is sealed, and if they are different, it is updated and the address is The tag AT is also updated and the updated address tag is also registered in the segment descriptor register. Further, in this embodiment, it is assumed that input/output operations are performed by an input/output control processor.

Additionally, for each I/O operation, if a process activates an I/O operation, the I/O control processor checks the segment associated with the activated I/O operation and updates the processor number in the associated segment descriptor. I'll keep it. Furthermore, in this embodiment, when a certain segment is used by several processes, an instruction for exclusive use of the segment and an instruction for releasing exclusive use of the segment are provided. .

When the processor executes this instruction, if this segment is not in use by another process, it registers the corresponding segment in the segment descriptor register within the processor. At this time, the processor number in the segment descriptor register is compared with the current processor number, and if they are different, the address tag is updated.

At the same time, it sets a bit indicating that the segment descriptor in main memory is exclusive to a certain process.
Upon release of exclusive use, the previously registered segment descriptor register is invalidated. If the address tag overflows when the address tag is updated as described above, the same process as in the first embodiment described above is performed. Further, in this embodiment, it is assumed that the virtual address also includes information regarding a process, and that certain information can be uniquely designated within the information processing system using the virtual address.

When accessing memory from the processor, the processor 7 uses the segment descriptor register SDR in the processor.
The processor outputs the segment address AS, address tag AT and write information W through the processor address register, stores these and the intra-segment displacement D in the processor address register, and requests the buffer memory 8 for the segment.

Regarding the following operations, the process number, which is the information unit for erasing in the first embodiment, replaces the segment address, and the access factor bit, which indicates whether the information may be written, is replaced by the processor number. The difference is that the value of the write bit of the address register is used, and if the necessary information is not found in the buffer memory 8, the real main memory address PA obtained from the segment address on the segment descriptor register is used as the main memory address PA. The second embodiment differs in that it is used when requesting a block transfer, but otherwise operates in the same manner as in the first embodiment.

Several embodiments of the present invention have been described above, but as is clear from these descriptions, the gist of the present invention is to avoid the possibility of content mismatch between the buffer memory and main memory due to process switching, etc. By switching the address tag attached to each information unit of information to be erased from the memory, effectively only the information that is likely to be rewritten and belongs to the information unit to be erased is erased from the buffer memory. The purpose of this is to eliminate the mismatch in content between the main memory and the buffer memory, and it is clear that several implementation methods are possible as long as they do not contradict this idea. For example, the number of address tag bits provided for each information unit for erasing can be selected as an appropriate value, and by giving a sufficiently long number of bits, it is possible to erase data by searching all sets of the buffer memory when the address tag value overflows. It is also possible to substantially eliminate the need to perform this process.

In addition, in the first embodiment, it was assumed that the process number and address tag are held by the processor, but it is not necessarily necessary to have such a configuration. It is also possible to arrange for these to be sent via the address line of the main memory when dispatching them. Further, in the first embodiment, the buffer memory is managed by real main memory addresses, but it may be managed by virtual addresses.

However, when transferring a block from the main memory when the necessary block does not exist in the buffer memory, control for accessing the main memory using a real address will be required.

Furthermore, if the virtual address does not include information regarding the process, it is sufficient to add a process number as in the first embodiment and manage the buffer memory using this.
It is obvious that if the virtual address already contains information about the process, this information can be used as the process number. Furthermore, in the second embodiment, it is assumed that the processor address register is provided with a write bit, but if the segment address contains information indicating whether or not the segment is a write-permitted segment. This information can also be used in place of the write bit.

In the above description of the embodiments of the present invention, the specific configuration of the control circuit is omitted because it is not directly related to the gist of the present invention, but it is clear that these can be realized by conventionally known methods. Probably. It also describes how to determine where to take a new block when a block is not found in the buffer memory, how to transfer blocks between main memory and buffer memory, how to handle valid bits related to this, and how to handle write operations. Since writing to the memory and the like are not directly related to the present invention, a description thereof is omitted, but these are performed by conventionally known methods. Additionally, when a process is dispatched, there is a special need to check the previously executed processor number and the current processor number in order to detect the possibility of content inconsistency due to the dispatch. Although hardware may be provided, it may also be realized by ordinary mechanical instructions or a microprogram.

In the first embodiment, in order to prevent content mismatches due to input operations from the input device, the processor updates the address tag when starting the input operation, or the input/output processor that performs the input/output operation performs this process. conduct.

Alternatively, there are several methods, such as when the input operation is completed and the process is dispatched to the processor, or when it is detected that the process has performed an input operation on the input/output processor just before. You may. Further, in the first embodiment, the process control block is provided in the main memory, but it would also be possible to provide a special memory location within the processor and store it there.

Furthermore, in the first embodiment, a special process is provided to handle data shared by several programs, and each program calls this process. Therefore, specific data can be processed simultaneously. Although it is assumed that multiple processes do not use the same data, in a system configured such that multiple processes access the same data on the main memory, the process is triggered when the data is locked, as in the second embodiment. By switching the address tags of the buffer memory and main memory, it is possible to prevent conflicts between the buffer memory and the main memory.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a first embodiment of the information processing system according to the present invention, and FIG. 2 is a block diagram showing a processor 7 in the second embodiment of the information processing system according to the present invention. In the figure, 1 is a processor address register, 2 is an address register, 3 is a management table, 4 is a buffer memory array, 511, 512, 513, 521, 522,
523, 6 is a control circuit, 7 is a processor, 8 is a buffer memory, and 9 is a main storage device. O2 diagram O diagram

Claims (1)

[Claims] 1. In an information processing system including a processor having a buffer memory that stores information on the main memory in units of blocks, an identification number of the information unit to be deleted from the buffer memory, an address tag corresponding to the identification number, and the information are stored in the memory address. means for adding write information indicating whether the unit is an information unit to be written; means for holding a current address tag and a processor number for which the information unit was most recently used for each of the information units; means for detecting a trigger related to a mismatch between the contents of the main memory and buffer memory using a held processor number and a current processor number; means for updating the address tag value at the detected trigger; and the information unit. The contents of the management table are searched using the name, the corresponding address tag, and the block address in the memory address, and if the write information is 1, the information unit name address tag and block address are the address of the address requested for access. A buffer memory having a means for accessing a block of the buffer memory corresponding to the information unit name and the block address when the write information is 0 and when the information unit name and the block address match together with each field is provided. By updating the address tag provided in the information unit for the buffer memory, an effect equivalent to erasing the information unit from the buffer memory is produced, thereby preventing the occurrence of logical contradictions caused by mismatch of contents between the main memory and the buffer memory. An information processing system characterized by: