JPS6037154A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS6037154A JPS6037154A JP58145376A JP14537683A JPS6037154A JP S6037154 A JPS6037154 A JP S6037154A JP 58145376 A JP58145376 A JP 58145376A JP 14537683 A JP14537683 A JP 14537683A JP S6037154 A JPS6037154 A JP S6037154A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- insulating layer
- gate electrode
- oxide film
- silicon oxide
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 12
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 238000000034 method Methods 0.000 claims abstract description 24
- 238000000151 deposition Methods 0.000 claims description 7
- 238000000992 sputter etching Methods 0.000 claims description 3
- 239000010410 layer Substances 0.000 abstract description 49
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 17
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 17
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 4
- 229910052782 aluminium Inorganic materials 0.000 abstract description 4
- 239000011229 interlayer Substances 0.000 abstract description 4
- 238000005530 etching Methods 0.000 abstract 3
- 238000005546 reactive sputtering Methods 0.000 abstract 3
- 239000011248 coating agent Substances 0.000 abstract 1
- 238000000576 coating method Methods 0.000 abstract 1
- 238000000206 photolithography Methods 0.000 abstract 1
- 238000007493 shaping process Methods 0.000 abstract 1
- 239000003990 capacitor Substances 0.000 description 11
- 238000002955 isolation Methods 0.000 description 5
- 239000000758 substrate Substances 0.000 description 5
- 230000015556 catabolic process Effects 0.000 description 3
- 230000001590 oxidative effect Effects 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- KWMLJOLKUYYJFJ-UHFFFAOYSA-N 2,3,4,5,6,7-Hexahydroxyheptanoic acid Chemical compound OCC(O)C(O)C(O)C(O)C(O)C(O)=O KWMLJOLKUYYJFJ-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- HXNZTJULPKRNPR-UHFFFAOYSA-N borinine Chemical compound B1=CC=CC=C1 HXNZTJULPKRNPR-UHFFFAOYSA-N 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229920006268 silicone film Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は半導体装置の製造方法、特にＭＯ８型半導体集
積回路装置に於ける多層導電層間の絶縁分離構造の製造
方法に係る。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing an insulation isolation structure between multilayer conductive layers in an MO8 type semiconductor integrated circuit device.
従来の代表的なＭＯ８型半導体集積回路に於ける多層導
電層間の絶縁分離構造の製造方法を、第１図に示すＭＯ
８型ダイナミックメモリのセル部を例にとり説明する。The manufacturing method of the insulating isolation structure between multilayer conductive layers in a typical conventional MO8 type semiconductor integrated circuit is shown in FIG.
This will be explained by taking the cell part of an 8-type dynamic memory as an example.
まず、Ｐ型の導電型を有するシリコン半導体基板１に周
知のシリコン屋化膜を用いた選択酸化の方法により、肉
厚の素子分離領域２を形成後、容量部ゲート絶縁膜を形
成する肉薄のシリコン酸化膜３を介して容量部電極を形
成する多結晶ボリンリコン層４をＣＶＤ法により被着し
た後、更にマスク酸化膜層５をＣＶＤ法によシ被着する
。First, a thick element isolation region 2 is formed on a silicon semiconductor substrate 1 having a P-type conductivity type by a selective oxidation method using a well-known silicone film. After a polycrystalline borin silicon layer 4 forming a capacitor electrode is deposited by CVD via a silicon oxide film 3, a mask oxide film layer 5 is further deposited by CVD.
その後、既知の光蝕刻及びシリコン酸化膜、多結晶ポリ
シリコンの異方向性プラズマエツチングの技術を用い、
ＭＯ８型ダイナミックメモリの容景部の電極４を形成す
る。更に、前記容量部ゲート絶縁膜３の不要の部分をエ
ツチングし、トランスファーゲート形成のため高温水蒸
気雰囲気中で熱酸化を行うことによシ得た肉薄のゲーＢ
４’ｌ化膜６を介し、ゲート電極７を形成する。その後
層間絶縁層１２を形成する工程、コンタクトホールを形
成する工程、アルミニウム配線層１４を形成する工程を
経て第１図に示すものを得る。Then, using known photoetching and anisotropic plasma etching techniques for silicon oxide film and polycrystalline polysilicon,
The electrode 4 of the scene part of the MO8 type dynamic memory is formed. Furthermore, the unnecessary portions of the capacitor gate insulating film 3 are etched, and a thin game layer B is obtained by thermally oxidizing the gate insulating film 3 in a high temperature steam atmosphere to form a transfer gate.
A gate electrode 7 is formed through the 4'l film 6. Thereafter, the process shown in FIG. 1 is obtained through a process of forming an interlayer insulating layer 12, a process of forming contact holes, and a process of forming an aluminum wiring layer 14.
しかるに、このような製造方法によるＭＯ８型ダイナミ
ックメモリセルの容量部ゲート電極４とトランスファー
ゲート電極７０間の絶縁耐圧は、前記トランスファ−ゲ
ート絶縁膜６形成時に同時に形成された前記容量部ゲー
ト電極４の側壁部のシリコン酸化膜の耐圧によシ決まる
。従って、メモリ容量の大容量化及び微細化を推進しよ
うとする場合、著しい歩留シ低下の原因となる。特に、
性能の向上を目さし、前記トランス７アーゲート絶縁膜
６を薄くしようとする場合、前記容量都電・極４と前記
トランス７アーゲート電極７間の十分な耐圧が得られな
いという問題が生ずる。However, the dielectric strength between the capacitor gate electrode 4 and the transfer gate electrode 70 of the MO8 type dynamic memory cell manufactured by such a manufacturing method is the same as that of the capacitor gate electrode 4 formed at the same time as the transfer gate insulating film 6 is formed. It is determined by the breakdown voltage of the silicon oxide film on the sidewall. Therefore, when attempting to increase the capacity and miniaturize the memory capacity, this causes a significant decrease in yield. especially,
When attempting to make the argate insulating film 6 of the transformer 7 thinner with the aim of improving performance, a problem arises in that a sufficient withstand voltage between the capacitor electrode 4 and the argate electrode 7 of the transformer 7 cannot be obtained.
本発明は、この容量部電極４とトランスファーゲート電
極７間の耐圧全向上することを目的とした半導体装置の
製造方法を提供するものである。The present invention provides a method for manufacturing a semiconductor device with the aim of completely improving the withstand voltage between the capacitor electrode 4 and the transfer gate electrode 7.
本発明によると、第１の導電層及び第１の絶縁層を重ね
て被着する工程と、前記第１の４．電層及び第１の絶縁
層を端部を整合して所望のパターンを形成する工程と、
第２の絶縁層を被着させる工により該第２の絶縁層の前
記第１の絶縁層と重なる部分を除去する工程と、第２の
導電層を被着する工程とを含むことを特徴とする半導体
装ｆ＾：の製造方法が得られる。According to the invention, the step of depositing a first conductive layer and a first insulating layer in a layered manner; aligning the ends of the electrical layer and the first insulating layer to form a desired pattern;
The method includes the steps of: removing a portion of the second insulating layer that overlaps with the first insulating layer by depositing a second insulating layer; and depositing a second conductive layer. A method for manufacturing a semiconductor device f^: is obtained.
以下本発明の実施例を図面全参照して詳糾１に説明する
。第２図（ａｌ （ｂＪ （句は、本発明をＭＯ８型ダ
イナミックラムの容量部の製造に適用した時の一実施例
の工程順の断面図を示す。Embodiments of the present invention will be described in detail below with reference to all the drawings. FIG. 2 (al(bJ)) shows a cross-sectional view of the process sequence of an embodiment when the present invention is applied to manufacturing a capacitive part of an MO8 type dynamic ram.
１ず、第２図（ａ）に示すようにｍｍ電型の半導体基板
ｌに公知のクリコン酸化ｊ模を用いた選択酸化の技術に
より肉厚の素子分離領域２を形成する。1. First, as shown in FIG. 2(a), a thick element isolation region 2 is formed on a semiconductor substrate 1 of mm type by a known selective oxidation technique using a known silicon oxide pattern.
シリコン窒化膜除去後、７ツ酸で処理することにより、
活性領域の半導体基板ｌを頭出させ、高温酸化雰囲気中
で熱酸化することにより、容量部ゲート酸化膜３を形成
する。次に第１の導電層として容量部ゲート電極４を形
成するため、ＣｖＤの技術を用い、ポリシリコン層を被
着する。リンを拡散することにより所望の？ｈ；導度を
得た後、ｌ史にＣＶＤの技術により、シリコン酸化膜層
を被着し光蝕刻及び異方向性リアクティブスパッタエツ
チングの技術を用い、容量部ゲート電極４、そし線層と
してシリコン酸化膜層９を被着した工程を示す。次に、
異方向性のＣＦ、を用いたりアクティブスパッタエツチ
ングの技術を用い前記シリコン酸化膜層９の絶縁層５と
重なる部分を除去することにより前記容量部ゲート電極
４の側面にのみ、シリコン酸化膜層１０．１１ 金残す
。以下第２の導電層とじてトランス７アーゲート電極７
を形成する工程、層間絶縁層１２ｆ：形成する工程、コ
ンタクトホール１３を形成する工程、アルミニウム配置
ｆＭＲ１Ｊを形成する工程を経て第２図（ｃ）に示すも
のを得る。After removing the silicon nitride film, by treating it with heptonic acid,
The capacitor gate oxide film 3 is formed by exposing the active region of the semiconductor substrate 1 and thermally oxidizing it in a high temperature oxidizing atmosphere. Next, in order to form the capacitor gate electrode 4 as a first conductive layer, a polysilicon layer is deposited using CvD technology. desired by diffusing phosphorus? h; After obtaining conductivity, a silicon oxide film layer is deposited using CVD technology, and then photoetching and anisotropic reactive sputter etching technology is used to form the capacitor gate electrode 4 and the line layer. The process of depositing a silicon oxide film layer 9 is shown. next,
The silicon oxide film layer 10 is formed only on the side surface of the capacitor gate electrode 4 by removing the portion of the silicon oxide film layer 9 that overlaps with the insulating layer 5 using anisotropic CF or active sputter etching technology. .11 Leave money. Hereinafter, the second conductive layer is referred to as the transformer 7 argate electrode 7
2(c) is obtained through the steps of forming the interlayer insulating layer 12f, forming the contact hole 13, and forming the aluminum arrangement fMR1J.
第２図（ＣＪに於いて、容量部ゲート電極４とトランス
ファーゲート電極７０間の絶縁は容量部ゲート電極４の
側面のシリコン酸化膜１０．１１及び前記容量部ゲート
電極４上のクリコン酸化膜５により保たれ、トランスフ
ァーゲート絶縁膜６の形成条件に依存せずに、十分な耐
圧を得ることができる。FIG. 2 (In CJ, the insulation between the capacitive part gate electrode 4 and the transfer gate electrode 70 is the silicon oxide film 10.11 on the side surface of the capacitive part gate electrode 4 and the silicon oxide film 5 on the capacitive part gate electrode 4. Therefore, a sufficient breakdown voltage can be obtained regardless of the formation conditions of the transfer gate insulating film 6.
本発明によシ第１の導電層のパターンの側面に、前記第
２の絶縁層を該第２の絶縁層の被泪時の膜厚と同程度残
すことができ、前記第１の導電層と前記第２の導電層間
に十分な耐圧をイ（Ｊることができる。従って、°メモ
リ容量の大容量化及び微細化を推進しようとする場合、
少なからぬ効果がある。According to the present invention, the second insulating layer can be left on the side surface of the pattern of the first conductive layer to the same extent as the thickness of the second insulating layer when wet, and the second insulating layer can be left on the side surface of the pattern of the first conductive layer. A sufficient breakdown voltage can be established between the conductive layer and the second conductive layer. Therefore, when trying to increase the memory capacity and miniaturize the memory capacity,
It has a considerable effect.
第１図は、ＭＯ８型ダイナミックラムの容量部の従来の
構造、を示す断面図、第２図（ａｌ （ｂｌ （ＣＩは
本発明の一実施例の工程順の断面図である。
ｌ・・・・・・−導電型半導体基板、２・・・・・・肉
厚の素子分離用シリコン酸化膜、３・・・・・・容量部
ゲート絶縁膜、４・・・・・・容量部ゲート電極、５・
・・・・・容１孔部ゲート電極上の絶縁膜、６・・・・
・・トランス７アーゲート絶縁膜、７・・・・・・トラ
ンスファーゲート電極、８・・・・−・前記−導電型半
導体基板と反対導電型を有する不純物層、９・・・・・
・シリコン酸化膜層、１０．１１・・１・・・前記容量
部ゲート電極側面のシリコン酸化膜層、１２・・・・・
・層間絶縁膜、１３・・・・・・コンタクトホール、１
４・・・・・・アルミ配線層。
ｈ／閃
（
（Ｃ）
、Ｆ７２図FIG. 1 is a sectional view showing the conventional structure of the capacitive part of an MO8 type dynamic ram, and FIG. 2 is a sectional view showing the process order of an embodiment of the present invention. ...-conductive semiconductor substrate, 2... thick silicon oxide film for element isolation, 3... capacitive part gate insulating film, 4... capacitive part gate Electrode, 5.
...Insulating film on the gate electrode of the hole 1, 6...
...Transformer 7 Argate insulating film, 7...Transfer gate electrode, 8...--Impurity layer having a conductivity type opposite to the -conductivity type semiconductor substrate, 9...
・Silicon oxide film layer, 10.11...1...Silicon oxide film layer on the side surface of the capacitor gate electrode, 12...
・Interlayer insulating film, 13...Contact hole, 1
4...Aluminum wiring layer. h/flash ((C), F72 figure
Claims (1)
、前記第１の導電層及び第１の絶縁層を端部を整合して
所望のパターンを形成する工程と、第２の絶縁層を被着
させる工程と、異方向性リアクティブスパッタエツチン
グにより該第２の絶縁層の前記第１の絶縁層と重なる部
分を除去する工程と、第２の導電層全被着する工程とを
含むことを特徴とする半導体装置の製造方法。depositing a first quaternary conductive layer and a first insulating layer in an overlapping manner; aligning edges of the first conductive layer and the first insulating layer to form a desired pattern; a step of depositing a second insulating layer, a step of removing a portion of the second insulating layer overlapping with the first insulating layer by anisotropic reactive sputter etching, and a step of completely depositing a second conductive layer. A method for manufacturing a semiconductor device, comprising the steps of:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58145376A JPS6037154A (en) | 1983-08-09 | 1983-08-09 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58145376A JPS6037154A (en) | 1983-08-09 | 1983-08-09 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6037154A true JPS6037154A (en) | 1985-02-26 |
Family
ID=15383797
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58145376A Pending JPS6037154A (en) | 1983-08-09 | 1983-08-09 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6037154A (en) |
-
1983
- 1983-08-09 JP JP58145376A patent/JPS6037154A/en active Pending
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