JPS603764A - Tracing system of execution state of program - Google Patents

Abstract

PURPOSE:To trace the execution state of a program having a dynamic overlap structure by providing a conversion buffer to convert an instruction execution address of the program to a corresponding address of a memory for trace. CONSTITUTION:A conversion buffer 10 is prepared which indicates the correspondence between program execution memory addresses of the program loaded to an overlay area of a program execution memory 2, namely, an overlap object program module and memory addresses 12 for trace allocated to the program. The instruction execution address of the program is converted to the corresponding memory address 12 for trace by the conversion buffer 10 to trace the execution state of the program having a dynamic overlay structure without restrictions of the structure of the overlaid area neither the number of overlay object modules. Dynamic overlay means that an optional overlay module is executed in an optional overlay area at an optional time.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a method for tracing the execution state of a program in a program-related product. On the other hand, when multiple program modules are arbitrarily overlaid, the j11 dynamic overlay structure is I'1
(Ideal for products with built-in programs) The program uses a 11-history trace method.

[The birth of invention]

In Takumi's 11i program product, the technology for knowing exactly which part of the program has been executed has been limited to the method shown below.

(1) A method for tracing rotation programs that do not have an overlay function. (2) For programs that perform overlay, the upper and lower limit 'γ addresses of each overlay area and the upper and lower limit addresses of the file memory are Register it as a table to recognize the program as being executed in the overlay area, and compare the Mt-te address with the registered address in this table. By doing this, the program structure line in the overlay area is recognized. However, in the case of these methods, it is impossible to trace programs that have overlays, and for I and B, the number of overlay areas and the number of program modules are large. The record was also very effective against dynamic overlays. Furthermore, we were unable to fully deal with Grograd, which has features that overlap and use parts of the overlay area.

[Purpose of the invention]

M-video product within the scope of the present invention 0) 7°°
'O! In the %RAM execution state tracing method, the number of overlaid areas for dynamic program overlay occurrences is 1JG OUTSU (lay property GLOSSIM module number will be 1Lflll poly begged, 1- The purpose is to provide a method for tracing the results.

[Invention: gL low]

The hunter of the present invention has an overlay of program execution memory.
A program that loads into the area (Overlay xL)
The correspondence between the memory address of the program module) and the trace memory address assigned to the program is 1. The immutable memory buffer is saved, and the actual address of the 10-gram instruction is 't'. tJ, by moving to the corresponding trace memory address in the buffer, the area to be overlaid is automatically raised. ．． In fact, the trace of the state of a program that has a %Jll-like auto-lay design is used as 01 bait.

[Embodiments of the invention]

FIG. 11 is a block diagram of one embodiment of the present invention.

1, a block 100 is a product with a built-in program, and is composed of a file memory 1, a program execution memory 2, and a processor 3 (for example, a microphone processor 7.c). The file memory 1 contains a host program and a large number of overlay program modules, while the host program 7 is a program host program and a large number of overlay program modules are stored in the memory 2 area.・The monoyl is loaded into the overlay area of the program memory 2 as needed and used.
J6 has a program structure that allows any overlay module to move in any overlay area in the programmable child memory z at any desired time, which is called a dynamic overlay structure.

When a program overlay operation occurs, a program (hereinafter referred to as "J") is executed to recognize the overlay. It is generally used to issue when output operation is performed for input/output km.
Figure 2 is an example of the format of the OUT command.
OIL T Hirogo was formed by the data department. Assign the value of this PORT ar number as a value indicating the actual lay operation, and add the identification g (ID#) of the overlay money program module in the data section.

In the example shown in Fig. 1, the program OAT (the OUT command that is fired at the 56th generation of the lay operation), the OUTSU that is overloaded by the addition of the OUT command, and the lay program monoil number By indexing Henmata Arpur from
A program sharpened by overlay teachers] 1. In order to deal with the problem, we created a conversion buffer that associates the execution memory address with the trace memory address, and thereby corrected the nature of the overlay program as the failed address of the module. It is possible to trace in a circle. Hereinafter, six blocks other than the program built-in product 100 with eight leads shown in FIG. 1 will be explained.

Block 4 in FIG. 1 is a 66-instruction decoding circuit that determines whether the instruction executed by the processor 8 is an OUT instruction, and 5 is an overlay program module identification circuit that determines whether an OUT instruction is determined. ■D: IE extraction circuit, 6 is 0. In the case of an instruction other than an IJT instruction, the node δ address (program execution memory
This is the address register that sets the address. 7 is the mN product 100 in the program.
++・1j register, 1 meoban i 4v't
It is assumed that the data is set from outside using the bus 113.

Block 8 is a conversion table having the number of entries corresponding to the program modules to be overlaid;
The entry includes the size of the program module, the program-Afj memory address, and the trace memory address.
The address is corrupted. . Here, it is assumed that the contents of the table 8 are registered in advance through the bus 116, either by external memory entry or by manual operation, before the trace is executed. Figure 8 shows the details of conversion 1 table 8, where ■ is the size of the overlay program module of the relevant entry, ■ is the execution memory address of the overlay program, and ■ is the number of entries in the overlay program. This is the trace memory address assigned.

The size δ of the overlay program module is defined as the size of the overlay program module by the module ``jlJ limit value 1 modulus n''.
, one; 1 section, and n1tj is 4'+ of the phrogram.
# Can be set as desired depending on the situation. Here, the Zolograt module division limit 11θ is mainly the rope, single address, and address of the overlaid program module, and the module division limit 11θ is
For example, if a module is loaded 250 bytes late, the maximum value is 256 and 7. C; Ql 0 Autolay program large module arrow "f memory 7' address (2) is overlay module or program l
；'I store gR product circle's program really-I memory 2 ”
r: IT 'i': Indicates the start address (loaded into the OAT<l/I area of the program execution memory 2), and points to the entry of the conversion buffer 10 described by this address. Trace memory
Address ■ indicates the beginning of the trace memory address corresponding to the overlay program module 1,
This address data is the value set by the size of the overlay module.
Ru.

However, when storing in the last entry of the fIK buffer 10, the trace memory address is stored while applying and changing the modulus n by n.

Returning to FIG. 1, block 9 is a variable return table/variable buffer tlilJ Point to the corresponding entry in the odd-smell cheagle 8, point the overlay module refresh rj memory address [/s■ in this entry to the entry in the conversion buffer lO1, and save the contents of the trace memory address ■ to the shock buffer. Store in lO.

At this time, the number of entries in the entertainment buffer 10 to be filled is determined by the value indicated by the dot in the overlay module. On the other hand, if the program does not have an overlay structure, the ID# sent via the bus 102
is invalid, and the conversion table 8's guide and trembling buffer 10
No registration will be made.

Block IO is a conversion buffer, and FIG. 4 shows its details. The memory buffer 10 has enough entries to cover all of the program execution memory troughs, and the six entries are divided into program execution memory 2 and program module division +m IL value units (e.g. 2.5
6 dots) vs. 1. i;, L-C is there. As shown in FIG. 4, the trace memory address lfr n:I'J is stored in the valley entry of the return buffer 10. However, this address is 11IL, which is divided by the division limit value "modulus n" of the overlay program Moanneal. All entries of this conversion buffer IO are initialized with the same trace memory address as the program execution memory address, and when a dynamic overlay occurs, the contents of the corresponding entry are changed to the trace memory address of the conversion table 8 by the control circuit 1169. The contents of memory address ■ will be rewritten by the size of the overlay module.

Block 1 shows an address conversion circuit. In this address modification circuit 11, the instruction address is divided into an intex part and a displacement part, and if the instruction address has an overlay structure, the instruction address is modified in the intex part of the instruction address.
GO) Point to the relevant entry and set the data of that entry in the upper part of the trace memory address register 12. If the program does not wait for the overlay Ii'ff m, the intex part of the instruction address is stored in the trace memory as is. - Set 1 to the upper part of address register 12. The displacement part of the instruction address is directly set in the lower part of the trace memory address register 12. The boundary between the intex part and the displacement part of the instruction address is equal to the entry of the transfer buffer 10, and the value of this boundary, 1 modulus n'', is the division limit value of the original program module, and the entry of the transfer buffer JO is Also, it has a different relationship with the size of the program module written as data in the Ajiji 41Q table 8. λ Number of entries in the conversion buffer - indicated by the entry in the conversion table - 4 - Size of the program module = Capacity trace memory for program execution area.The trace memory 14 stores the line status of all program modules in the file memory 1. There is an α program in file memory 1.
The correspondence between the module and the trace area in the trace memory 14 is determined by the table 8, and the 6-code match (Kitaka address) to trace of the corresponding program module is determined.
The battle with Area Tani'4Jya is in conversion buffer 10) f
z will be done. 6 bits of trace memory 14 also consist of 1 bit;
Assume that due to constraint 1, '1'° or ↑;t is written into the corresponding area of the trace memory 14 in response to the instruction (I).

This is a vague translation of the entire operation in Figure 1. Instructions executed by the processor 8 follow a path 101 and enter the instruction decode circuit 4. The instruction decode circuit 4 checks whether the instruction is an OUT instruction or not, and if it is an OUT instruction, the overlay program module ↓ - 7 in the data section is
Separate arrival number (ID#) or ID? It is detected by the output circuit 5.

The HD#f shell output 11 also enters the greeting table/transformation buffer control intermediate circuit υ through the rDlti path 102 commonly used in 5. Hentai Table/Hentai Buffer 11flJ
1il 1 time Il after 9, pass 114 beg river and become 11
Looking at the contents of the 11 register 7, if the data indicating that the program has an overlay structure is set in the corresponding 11111 register 7, the 11) I+- sent along the path 102 is invalid. Toshi, Henkyo Table 80
Examination and registration of the pedestal buffer lO7\ are not performed. In other words, 0LIT is a ρ-contraction of how many 54 times the output is produced for the human output iron fR that is ddd by the processor, and by checking the contents of register 7, , when an OUT prevention command is issued, it is determined whether the May Valley operation is ノJ(SUOUT +6 command〃・6).

1lflJ-If the data that has an overlay structure is set in register 7, the conversion table/change coal batn V + 1ilJ conversion 16 & 9 is manually created IJ)
# > Original path 104) QI and convert table 8
Point to the corresponding work/tree and check the size of the overlay program module stored in that entry.
, Overlay program module lol What memory address ■, Memory address for tracing ■ Beg Has 105
Follow and enter. Then, in the nl, R-table/henmo buffer control circuit 9, the overlay program module execution memory address ■ of the entry input from the conversion table 8 points to the corresponding entry in the conversion buffer lO, and the Mim (M=
1, 2...m) through the path 106, trace memory address 01 (■),
0□(■17 modulus n),...On(■+modulus nX (m -1) is stored 1-.

Now the overlay area consisting of the program execution memory 2 will be displayed.For the overlaid program module, the correspondence between the program execution end memory address and the trace memory address will be registered in the conversion buffer 10. The correspondence between the program execution memory address and the trace memory address for the parked program is that all entries in the change buffer lO have the same trace memory address as the program execution memory address.・Adleske paddy season leg) ^ Kotore Tore de 1
After that, it will never be <5:+74 f.

Instructions are executed in processor v8, 6r + total code 1j
JJ No overlay operation at 4 OUT f=6
Whenever it is detected that it is not bamboo, the execution memory address (verification address) of the corresponding 66 instructions is set in the instruction address register 6. This means, for example, that the decoding circuit immediately removes the path 110 from the processor 8 and manually retrieves the fetch address before adding the command. This is achieved by transferring the manually entered instruction fetch address to the instruction address register 6 when it is detected that the OUT to instruction is 1 good.

The address conversion circuit 11 manually inputs the 6δ order address set in the erasure address register 6 through the path 108, and converts the program module division limit increase value (modulus nL & point to the index part and displacement of the relevant node address). The division into the index part and the displacement part by the modulus n determines the number of elements in the conversion packer 10, and the n value can be set arbitrarily within the apparatus.

The contents of control register 7 are also provided to address conversion circuit 11 through path 115. Address conversion circuit 11
Now, if data indicating that the program does not have an overlay structure is set in the control register 7, the index part of the group address is directly set in the upper part of the trace memory address register 12 through the path 108. Also, if data indicating that the control register 7 has an overlay structure is set, the index part of the instruction address is sent to the conversion buffer 1.0 through the path 10.
, point the corresponding entry in the conversion buffer 10 in the index field, and transfer the contents of the entry to the path 109.
is set in the upper part of the trace memory address register J2. Tracing memory address register] 2, the displacement part of the instruction address is passed through 110.
Set it through. The contents of the trace memory address register J2 are input to the trace memory control circuit 13 via a path 111. In the trace memory control circuit 13, trace memory address register J
A logical ``1'' is written to the corresponding address of the trace memory 14 indicated by 2 through the path 112.The trace memory 14 has enough capacity to cover all the program modules in the file memory l. Every time an arbitrary instruction of the resident program or overlay program module in the file memory l is executed by the processor 3, 1 is stored at the corresponding address in the trace memory 14.
” is written. Therefore, by reading the contents of the trace memory 14, the file memory 1
Even when programs and programs are dynamically overlaid, it is possible to grasp the executed/unexecuted portions corresponding to valley programs and modules.

In this embodiment, dynamic overlay execution is
Although the method is described in which recognition is performed using the UU'l' command having the ott'r number, other instruction codes may be used as long as the instruction decoding circuit 4 can execute dynamic overlay. Furthermore, in this example,
Dynamic overlay 4I? In the case of a program that has an I structure, the program execution memory address and trace memory address are all address-converted, including non-overlay areas (resident areas); For non-overlay areas, the memory address for tracing may be determined by non-address translation.

Furthermore, in this embodiment, the conversion table 8 is pointed to by the ID# of the "U C1i" instruction executed when a program overlay operation occurs, and the size of the overlaid program module and the overlay program execution memory are determined.・I tried to obtain the address and trace memory address, but these data are not available during overlay operation.
It may also be obtained from the processor 3, in which case the conversion table 8 is unnecessary.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, the following effects can be obtained.

(1) It is possible to handle programs with dynamic overlays. Furthermore, it is possible to collect traces of the occurrence of overlays using the actual operating time of the internal program of the product to be traced.

(2) It is possible to deal with complex programs that have conventionally been difficult to deal with, such as multi-purpose volleyball numbers, multi-purpose volleyball program modules, or fI copying with overlapping overlay areas. be.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a diagram showing the formatting of the υLl1' instruction that is executed when an overlay occurs, and FIG. 3 shows details of the conversion table. The figure shown in FIG. 4 is a diagram showing details of the conversion buffer. l...File memory, 2...Program execution memory, 3...Processor, 4...Instruction decoding circuit, 5...I IJ# detection circuit, 6...Kinto address ° register, 7... Control register, 8... Conversion table, 9... Conversion table/conversion
J control circuit, 10... Conversion buffer, 11... Address conversion circuit, J2... Trace memory address.
Register, 13... Trace memory control circuit, 14
...Trace memory. Representative Patent Attorney Makoto Suzuki-371-'#-,,c1 t+4 ・Electronic ＼ viewing ・-ra (

Claims (1)

[Claims] 111 Program ``Program in a program-related product that has an overlay area in an execution memory and executes an arbitrary program module from a number of program modules by overlaying it on the overlay area. A method for tracing the execution status of
A trace memory configured to map a plurality of program modules, and a program execution memory address and a trace memory address of a program module overlaid in the overlay area of i4iJm's own program execution memory. A conversion buffer indicating the correspondence is provided, and the program memory address of the executed instruction is converted into a corresponding trace memory address by the conversion buffer, and the trace memory address indicated by the trace memory address is Corresponding number in memory, L1i! A method for tracing the execution status of a program, characterized by recording data indicating the execution of a KgiJki order. (2) When a program overlay operation occurs, the contents of the forward self-transforming buffer include the size of the program module, the overlaid program execution memory address, and the trace memory address allocated to the program module. 2. The program execution state tracing method according to claim 1, wherein the program execution state tracing method is created by obtaining an address. (31f) Provide a conversion buffer having a K'r- entry corresponding to a program module, and in which the size of the program module, the program execution memory address, and the trace memory address are set to 41 in the + entry; The size of the overlaid program module is determined by voiding/tossing the corresponding entry in the conversion buffer based on program module identification information indicated by a specific instruction executed when a program overlay operation occurs;
3. The program execution state tracing method according to claim 2, wherein a program execution memory address and a tracing memory address are obtained.