JPS6037774A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To reduce the distance between a base electrode take-out region and an emitter layer by a method wherein the base electrode is led out by means of the double layer of a poly Si film and a metallic silicide film, and then formed on an isolation oxide film adjacent to the base layer. CONSTITUTION:After an n<+> type collector buried layer 2 and an n<-> type epitaxial layer 3 are formed in a p<-> type Si substrate 1, a p type layer 6 serving as the active base layer is formed. Next, a poly Si layer 601 is formed over the entire surface. Then, the layer 6 is made as the active base region 61, and thereafter poly Si films 602 and 603 are adhered. An n<+> layer 71 to serve as the emitter layer and an n<+> layer 81 as a collector electrode take-out layer are formed. The films 602 and 603 are selectively etched and then oxidized, thus forming oxide films 107-109. The films 106-109 are partly removed by anisotropical etching. Thereby, the film 107 on the side surface of the films 602 and 603 remains. Metallic silicide films 501-504 are formed. Finally, each electrode wiring 9-11 is formed after each electrode hole 50, 70, and 80 of the base, emitter and collector is formed.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a method for manufacturing a semiconductor device, and in particular to an improvement in a method for forming an 'Ik lead-out portion of a transistor in a bipolar semiconductor integrated circuit device (hereinafter referred to as "rBrp rC"). This is related to.

[Prior art]

In general, transistors in BIP ICs are usually formed in electrically independent islands by oxide film isolation using pnn junction isolation single selective oxidation technology, or by a method using triple diffusion. Here, we will discuss the case of forming an npn (npn) transistor using the oxide film separation method.

Of course, the present invention can also be applied to cases where the above-mentioned separation methods other than the above are used, or to cases where 1) nl)) transistors are formed.

Figures 1←) to e) are cross-sectional views showing the main process steps of the conventional preparation method. First, p with a low impurity concentration
After selectively forming a highly impurity n-type (n+ type) FI (2) to serve as a collector buried layer on a p-type (p-type) silicon substrate O), an n-type epitaxial layer (
3) to grow (Fig. 1(a)). Next, using the nitride film (201) formed on the underlying oxide film (101) as a mask, a thick isolation oxide film (102) is formed by selective oxidation. At the same time, a p-type layer (4) for channel cutting is formed (
Figure 1Φ)). Next, the nitride film (201) used as a mask for the selective oxidation is removed along with the underlying oxide film (IOI), an oxide film (103) for ion implantation and retention is formed, and a photoresist film ( Using the photoresist film (not shown at this stage) as a mask, form the p+ type layer (5) which will become the external base layer.

Furthermore, this photoresist film is removed, a new photoresist film (301) is formed on each, and using this as a mask, a p-type layer (6) which will become an active base layer is formed by ion implantation. ). Subsequently, the photoresist film (301) is removed, and a passivation film (generally made of phosphosilicate glass (PSG)) is removed.
401) Pace ion implantation P (53
, (6) and form the required openings (70) and (80) in the PSG film (401), and then form a Siemitter layer by ion implantation. Form an n+ type layer (8) which is to become a multilayer layer (FIG. 1(d)).Then, each ion implantation layer is annealed to form an external base layer (52) and an active base layer (62). In addition to completing the emitter layer (T1)
Then, a collector electrode number protrusion layer (81) is formed, and an opening (50) for taking out the base electrode is formed.
M. Use metal silicide (platinum silicide (PT SI) or palladium silicide (PTSI) or palladium silicide (PTSI) to prevent electrode puncture).
9), emitter electrode wiring (10), and FIG. 2 is a plan pattern diagram of a transistor manufactured by this conventional method.

By the way, the frequency characteristics of a transistor depend on the pace collector capacitance and pace resistance, etc., and it is necessary to reduce these in order to improve the frequency characteristics. Although an external base layer (52) was provided, this had the disadvantage of increasing the pace collector capacity.
The pace resistance also depends on the distance D1 between the emitter layer (11) and the opening (50) for taking out the base electrode, and in this conventional structure, the distance between the pace electrode wiring (9) and the emitter electrode wiring (10), These arrangements (9) t (1
This is the total distance of the protrusion from each opening (5G) and (70) of 0).Even if the accuracy of photoetching is improved and the electrode wiring spacing is reduced, this protrusion will inevitably remain. It was something to put away.

[Summary of the invention]

The present invention addresses these drawbacks of the prior art and directly extracts the active base from the active base region through the base layer, thereby increasing the distance between the emitter layer and the base electrode opening.
The distance is shortened without incorporating the protrusion from each opening of each electrode wiring, and at the same time, the base-collector capacitance is increased without using an external base layer with a high impurity concentration. The purpose of the present invention is to provide a method for manufacturing a semiconductor device that does not cause the above-mentioned problems.

[Embodiments of the invention]

Hereinafter, one embodiment of the method of this invention will be explained in Figures 3 to 6.
This will be explained in detail with reference to the drawings.

FIGS. 3(0) to 3(f) are cross-sectional views showing the main process steps of the method of this embodiment, and the same reference numerals as in the conventional example represent the same parts or equivalent parts.

In this embodiment method, the p-type silicon substrate (1
), an n''-type collector buried layer (2), an n-type epitaxial layer 0), a p-type layer for channel cut 0), and an oxide film for isolation (102) were formed on the layer shown in FIG.
Nitride film (201) and underlying oxide film (101) in b)
Then, an oxide film (103) is formed for ion implantation, and the active base layer and p-type layer (6) are removed through a photoresist mask (not shown). The oxide film (103) in the vicinity of the area that should become the open part of the base electrode 11A is removed, and a polysilicon film (601) is deposited on the entire surface including the removed part (1). Figure 3(a)). Next, p-type impurities are introduced into the entire surface of this polysilicon layer (601) and sintered to form the p-type layer (6) into an intermediate active base region (61).
), the polysilicon hx4 (601) is selectively etched and removed by shift 1, and oxidized again to form t1ε v(105) at the position where the oxide film (103) was located.
The second oxide film of the remaining polysilicon film (601)
o6), and furthermore, Psc IFi￥(4
01) (Fig. 3 Φ)).

Next, by selective etching using a photoresist mask (not shown), the oxide film (105) and the PSG film in the areas to become the emitter layer and the collector electrode extraction layer are etched.
The polysilicon film (401) is removed, the polysilicon films (602) and (603) are covered, and each polysilicon film (603) is covered with tf.
After ion-implanting n-type impurities at a high concentration into (602) and (603), driving is performed to diffuse them to form an n+-type layer (71) to become an emitter layer and an n-type layer to become a collector electrode region protruding layer. (81) is formed (Fig. 3(C)). Next, selective etching is performed to leave only the portions of the polysilicon films (602) and (603) that have become diffusion sources, followed by oxidation to remove the sides of each of the polysilicon films (602) and (603). Silicone films (107) and (10B) are formed on the surface and the upper surface.
109) (Fig. 3(d)).

Next, each polysilicon film (602) is used to form the emitter layer and the collector electrode extraction layer.

Part of (603) and oxidation 1 on the collector-base junction
(106) and a resist film (302),
And, using each polysilicon M (602) and (603) as a partial mask, the base contact and the oxide film (106) on the polysilicon film (601) following this,
Psc film (401) and polysilicon film (602)
, (603) Top/7-1'DD Ik lIB /
1 no 'S (10o) small part b II-thing*t
:Removed by etching. By using this anisotropic etching, the polysilicon film (602)
.

The oxide film (107) formed on the side surface of (603) remains without being etched (FIG. 3(e)). Next, a metal layer (shown in the figure) of Pj+Pd, TitW+MO, etc., for forming metal silicide between silicon and polysilicon film, is formed on the entire surface by evaporation or sputtering, and then sintered. and metal silicide films (501), (502), (503) respectively.
and (504), the exposed surface of the silicon substrate and the polysilicon film (601), (602) and (603)
This metal layer is removed by etching with aqua regia, leaving only the metal silicide layer, and then a passivation oxide film or nitride film (
202), and then selectively etching the nitride film (202) to form a base electrode contact hole (5).
After forming the emitter electrode contact hole (70) and the collector electrode contact hole (80), the base electrode wiring (9) is formed using a resistance metal such as At.
), an emitter electrode wiring (10) and a collector N-pole arrangement (11) are formed respectively (Fig. 3 σ)).

FIG. 4 is a plane pattern diagram of a transistor manufactured by the embodiment method as described above, which corresponds to the conventional method shown in FIG. 2, and as is clear from FIG. Polysilicon film (601) and metal silicide film (501) connected to electrode (9)
The window opening for diffusion is determined by the overlapping part of the polysilicon 1i (602) that serves as the diffusion source, so the distance between the two is shown in Figure 2 for the conventional method. The distance DI can be made smaller than the distance DI, which not only reduces the base resistance by that amount, but also reduces the distance DI in place of the conventional p+ type external base layer (52) (several tens of Ω/hole to 100 Ω/hole).
Metal silicide film (501) with specific resistance to (several Ω/mouth ~
The base layer (62
) itself is slightly smaller, the pace◆collector capacitance also becomes smaller, improving the frequency characteristics of the transistor.

Note that a nitride film (202) is used as a coating when forming contact holes.
was used because the PSG film (401) acts as a stopper 17 when etching the opening in the nitride film (202).
The opening of 01) can also be made slightly larger. However, by sufficiently controlling the etching of the contact hole, an oxide film such as a PSG film may be used instead of the nitride film.

Furthermore, the emitter diffusion layer (71) is connected to the electrode (
10), it is possible to configure the transistor as shown in FIGS. 5 and 6 as a way to further reduce the base resistance. That is, by forming a metal silicide film (501) connected to the base electrode from three sides around the emitter diffusion layer (71),
The base resistance can be reduced to less than half that of the case shown in FIG. Also, the distance in FIG. 4 may vary depending on the overlay accuracy in photolithography during etching of the polysilicon film (602). For example, due to the design, 21trn
The accuracy (including etching) is ±1.
If it is 0 μm, Da = 1 μm to 3 μm, but if a metal silicide film (501) is formed for the emitter diffusion layer (71) K as shown in FIG.

Furthermore, even if an emitter diffusion layer (71) is added as shown in FIG.
), it is possible to lower the base resistance as usual without placing a base contact and electrical connection between this additional emitter diffusion layer as in the conventional method. This can be achieved without significantly increasing the base area.

〔Effect of the invention〕

As detailed above, according to the method of the present invention, the base electrode is drawn out by a double layer of a polysilicon film and a metal silicide film, and this is connected to an isolation oxide film adjacent to the base layer.
Since the distance r1 [() between the space electrode number extraction region and the emitter layer can be reduced and the base resistance can be reduced, and since an external base layer with a high impurity concentration is not provided, the base collector It is possible to reduce the capacitance between
It has the advantage of being able to obtain transistors with good characteristics.

[Brief explanation of the drawing]

1(a) to 1(e) are cross-sectional views sequentially showing states at the main process steps of a conventional manufacturing method, FIG. 2(a) is a plane pattern diagram of a transistor manufactured by the conventional method, and FIG. Figures (a) to f) are cross-sectional views sequentially showing states at the main process steps of a manufacturing method according to an embodiment of the present invention, and Figure 4 is a planar pattern diagram of a transistor manufactured by the method of the above embodiment. 5 and 6 are plan pattern diagrams showing special modifications of the transistor in FIG. 4, respectively. (1)...p-type silicon substrate, (3)...I
'l-type epitaxial layer (first conductivity type layer), (6
), (61). (62)...Base layer, ff), (71)...
Emitter a, (8) p (81)...Collector electrode extraction layer, (9)...Base electrode, (10)...
... Emitter electrode, (11) ... Collector electrode,
(102)...Isolation oxide film, (101), (105
), (106). (107), (10B), (109)...silicon oxide film, (201), (202)...Φ/nitride film,
(302)・Kaikushi・Resist film, (401)・・・P
SG membrane, (600). (601), (602)...Silicon film, (5
00). (501)t (502), (503)...Gold scrap silicide film. Agent Yumi Oiwa 1 Figure 1 Figure 2 Figure 3 Figure 3' Procedure correction! F (Voluntary) Showa Ta/Yata Month Brother (3. Relationship with the case of the person making the amendment Patent, IJ temporary (i person location Marunouchi 2, Chiyo 111-ku, Tokyo) 1I 2 a
c'3.5; Name (601) = Ryodenki Co., Ltd. Representative Kata 111 Jin Hachibu 4; Agent fl;
No. 2: 3-wing violation of the detailed description of the invention in the specifications of Mitsubishi Electric Corporation

Claims (1)

[Scope of Claims] α) A first step of forming a first conductivity type layer surrounded by an isolation region on the surface of the semiconductor substrate and serving as one collector region; a second step of forming a base layer of two conductivity types; a third step of forming a silicon film from part of the base layer to an isolation region in contact with the base layer; On the surface of the conductivity type layer,
and a fourth step of forming a silicon oxide film on the silicon film, and a fifth step of removing by selective etching each portion of the silicon oxide film where an emitter layer and a collector electrode area protruding layer are to be formed. After this step, a silicon film is formed and impurities of the first conductivity type are introduced at a high concentration, and the introduced impurities are diffused into the base layer corresponding to each part by annealing to form the emitter layer and collector electrode area. a sixth step of forming an extrusion layer; a seventh step of selectively removing a portion of the silicon film other than a portion covering the emitter layer and the extrusion layer in the collector electrode area; and forming a silicon oxide layer on the silicon film. The eighth step is to form a silicon oxide film on the collector base junction, and the part other than the part covering the same junction side of the silicon film on the emitter layer and the collector electrode area extension layer is etched by anisotropic etching. A ninth step of selectively removing the silicon film, the silicon film on the space electrode number extraction region, the emitter layer, and the collector electrode extraction layer. and a tenth step of forming a metal silicide film on each of the silicon films on the base layer, and forming an insulating film on the separation region and the region surrounded by the separation region and subjected to each of the above steps. A base electrode is formed at the silicon film position, an emitter electrode is formed at the emitter layer position, and a collector 1! is formed through the opening formed in each protective film. An eleventh step in which collector electrodes are formed at the positions of the pole extraction layers, respectively.
A method for manufacturing a semiconductor device, comprising the steps of: (2) Polycrystalline silicon is used as the silicon film, and in the third step, a polycrystalline silicon film is formed on the entire surface, and after introducing impurities of the second conductivity type, an interlayer is formed from a part of the base layer. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the patterning is carried out so as to remain over the isolation region in contact with the isolation region.