JPS61108162A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To reduce base.collector capacity and base resistance for the improvement of frequency characteristics by a method wherein a base electrode is connected to its base region through the intermediary of a two-layer lamination of an Si film and a metal silicide film. CONSTITUTION:On a p<-> type Si substrate 10, an n<+> type collector buried layer 30, n<-> type epitaxial layer 20 are formed. Thereafter, a p type layer 60 to be an activation base region and a guard ring layer 61 are formed, whereupon a polycrystalline Si layer 601 is formed. Polycrystalline Si layers are then formed in the resistance-forming region and wire-forming regions. In the layer 60, an n<+> type layer 80 to be developed into an emitter region is formed. In the layer 20, an n<+> type layer 81 to be developed into a collector electrode leading-out layer is formed. Next, a metal silicide film 501 is formed, to cover the exposed surface of the Si substrate 10, layer 601, and an each of the polycrystalline Si layers. Next, contact holes 70-72 are provided for base, emitter, collector electrodes, and electrode wirings 91-93 are formed for the base, emitter, collector. With the base electrode being built on the film 501 positioned on the film 601, the capacity between base and collector and the resistance of the base may be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device 1 and a method for manufacturing the same, and particularly relates to a bipolar semiconductor integrated circuit device (1-semiconductor integrated circuit device, BIP-
The present invention relates to a transistor in an IC (hereinafter referred to as an IC), more specifically a transistor clamped by a Schottky barrier diode (hereinafter referred to as an SBD), and several stages of a method for forming an electrode lead-out portion thereof.

[Prior art] Generally, in BIP-IC] the transistor has a pO
Junction isolation, oxide film isolation using selective oxidation technology, or 3
They are formed in electrically independent islands by a method using heavy diffusion, etc. Here, a method for forming an npn transistor by an oxide film method will be described. Of course, when using the above-mentioned various separation methods other than this, it can also be applied to pnp t-transistors.

On the other hand, in a high-speed 1] thick circuit using a 1-hyeon resistor in a B I l) IC, in order to reduce the saturation of the 1-hyeon resistor, the collector C
・Transistor 1 with 5BD2 clamped between base 8
is used, generally 5-TTL (S ChOtliky
1'ansfsjor Transistor L
0(lic)T)1. S-'I-Wing L (1-1)Il
It is widely used in logic ICs such as lpo+*er5TTL).

The transistor 1 clamped with 5BD2 as described above has been conventionally manufactured by the Jti method shown in FIGS. 6A to 6F, and the conventional method will be explained below based on these figures. First, as shown in FIG. 6A, an n-type (n+-type) layer 20 with a high impurity concentration is selectively formed on a p-type (p-type) silicon substrate 10 with a low impurity concentration. After that, an n-type epitaxial layer 30 is grown on them. Next, as shown in FIG. 6B, an underlying oxide film 101 and a nitride film 201 are grown on the 0-type epitaxial layer 30. A thick isolation oxide film 102 is formed by patterning the nitride film 201 and performing selective oxidation using the nitride film 201 as a mask.
Under the M oxide film 102, there is a p-type layer 1 for channel force/isolation.
40 are formed simultaneously.

Next, as shown in FIG. 2C, the nitrided [I201] used as a mask for the above-mentioned selective oxidation was replaced with the underlying oxidized 111101.
oxide film 1 for ion implantation protection.
03 is formed on the n-type epitaxial W30, and a photoresist 111! (The 7-photoresist film at this stage is not shown) is used as a mask to form a p+ type [250, 51] which will become an external base layer and a guard ring layer of the SBD.

Further, the above-mentioned photoresist film is removed, a new photoresist film 301 is formed, and using this as a mask, a p-type layer 60 which becomes an active base layer is formed by ion implantation.

Subsequently, as shown in FIG. 6D, a photoresist film 301 is formed.
is removed, generally using phosphosilicate glass (PSG).
) is deposited on the base ion-implanted layer 50.
After performing heat treatment that also serves as baking and tightening to form an intermediate stage external base 1150 and active base layer 60, P
The required openings 70 and 71 are formed in SGpA401, and the 11+ which is to become the emitter layer is formed by ion implantation.
Next to the mold layer 80, an n+ type layer 81 which is to become a collector electrode extraction layer is formed. In the process, as shown in FIG. 6E, each ion implantation layer is annealed to complete the external base 1i 150 and active base layer 60, as well as to take out the emitter layer 80 and the rectifier electrode! 1181 is formed.
SG film 401 has a hole for extracting the base electrode and SB
A flowering part 72 that becomes a 11°C hole for D is formed, and each flowering part 7
At 0.71 and 72, metal silicide [platinum silicide (Pt-8i)] was added to prevent electrode protrusion IM tJ.
, palladium silicide (Pd-8t> etc.) film 50
form 1. At this time, in the opening 72, the n-type epitaxial layer 11130 and the metal silicide film 5 thereon are formed.
01 to form an SBD. Thereafter, the metal silicide l11501 J: is coated with the base electrode wiring 91. Emitter electrode arrangement i+92 and collector electrode wiring 93 are formed.

Further, similar steps are performed again in the resistance formation region ti11 and the wiring formation region.

A semiconductor device including a semiconductor element clamped by a conventional SBD has been formed through the steps described above.

[Problems to be Solved by the Invention] FIG. 7 is a plan pattern diagram of a transistor manufactured by this conventional method. The frequency characteristics of a transistor depend on the base-collector capacitance I, base resistance, etc., and must be made extremely small in order to improve the frequency characteristics. However, in the structure described in -1-, p+
Although a mold external base layer 50@ is provided, this has the disadvantage of increasing the base-collector capacitance. Also,
The base resistance also depends on the distance 1111D+ (shown in FIG. 7) between the emitter 1180 and the base electrode opening 72, and in the conventional semiconductor device, the distance between the base electrode wiring 91 and the emitter electrode wiring 92 and the distance between each electrode wiring 91 , 92 and the protruding distance from each opening 72. There was a limit to what I could do.

Furthermore, in addition to the manufacturing process of the element section, processes for resistors and wiring for the actual device had to be added, making the process complicated.

SUMMARY OF THE INVENTION An object of the present invention is to eliminate the above-mentioned drawbacks and to provide a method for manufacturing a semiconductor device clamped with an SBD having favorable frequency characteristics and a simplified manufacturing process.

[Means for Solving the Problems] In a semiconductor device including a semiconductor element clamped by an SBD according to the present invention, when connected to a part of the guard ring layer of a Schottky barrier diode, it also extends to an isolation region. A metal silicide film forming a Schottky barrier diode is formed on a portion of the base region, the guard ring layer and the silicon layer, and a base electrode is formed on the metal silicide film on the silicon film.

In the manufacturing process of a semiconductor device, which is another aspect of the present invention, in the metal silicide forming process of a contact portion necessary for forming an electrode for transistor mounting, a resistor and a wiring are formed at the same time as the metal silicide film is formed,
Resistors and wiring electrodes are formed in parallel with the manufacturing of the element section.

[Function] Since the base electrode is connected to the base region through the stacked layer of silicon film and metal silicide film, an external base layer with a high impurity concentration is unnecessary, and base resistance and base collector capacitance can be reduced. can. Furthermore, since the distance between the base electrode lead-out area and the mitter area becomes small, there is no need to consider the protrusion of each electrode wiring from each opening.

Furthermore, since the resistor and the wiring N-pole are formed in parallel with the manufacturing process of the element portion, the lit manufacturing process of the semiconductor device is simplified.

[Embodiments of the invention] Figures 2A to 2G, 3A to 3F, and 4
Figures A to 4F are cross-sectional views showing the main process steps of a manufacturing method according to an embodiment of the present invention. FIG. 4 shows the manufacturing process of the wiring area. First, the 6th
Up to the state shown in FIG. P-type layer 40 for channel cut and oxidized ml for separation! After forming 1102, the nitrided IM (201) and the underlying oxide film 101 shown in FIG. 6B are removed, and as shown in FIG. , a p-type layer 60, which forms the active base region, through a photoresist mask (not shown).
The guard ring layer 61 etc. of the BD are formed by the injection method, and the oxide film 10 in the area where the base electrode opening is to be formed is formed.
3 is removed, and a polysilicon film 601 is deposited on the entire upper surface including the removed portion. At this time, a polysilicon film 602°60
3 is formed. (See Figures 3A and 4A).

Next, as shown in FIG. 2B, this polysilicon II
After introducing p-type impurities into the entire surface of the polysilicon film 601, sintering is performed to make the p-type layer 60 an intermediate active base region 60, and then the polysilicon film 601 is removed by selective etching.

At the same time, as shown in FIGS. 3A and 4A, selective etching is also performed in the resistor formation region and wiring formation region, leaving polysilicon films 602 and 603. Next, oxidation is performed again to form III oxide 105 where the oxide film 103 was, and the remaining polysilicon film 601.
．． Oxide 11106 is formed on -1- of 602 and 603, and a PEG film 401 is further formed on the entire upper surface.

Next, as shown in FIGS. 2C, 3B, and 4B,
By selective etching using a photoresist mask 302, the polysilicon film 601 and 603 except for the polysilicon film 602 which will become the resistor formation region shown in FIG. 3B are etched.
A region that should become an emitter layer and a collector electrode extraction layer,
and oxide films 105 and 106 on the isolation oxide film 102
Then, the PSG film 401 is removed. Next, as shown in FIGS. 2D, 3C, and 4C, a new photoresist Il$303 is used to form the area where the base electrode part and SBD will be formed, and the entire area shown in FIGS. 3 and 4. After covering the
N-type impurities are ion-implanted at a high concentration to form an n+-type layer 80 that will become an emitter region and an n+-type layer 81 that will become a collector electrode extraction layer.

Next, as shown in FIGS. 2E, 3D, and 4D, after removing the photoresist masks 302 and 303,
After forming a metal layer 500 that forms metal silicide between silicon layers such as Pi, Pd, Ti, W, and Mo on the entire upper surface by vapor deposition or sputtering, sintering is performed to form a metal silicide film 501 on the exposed surface of the silicon substrate. and polysilicon films 601, 602 and 603
The active base region 60, S
BD area, emitter area 80, J: and collector area t*8
form 1.

Next, as shown in FIGS. 2F, 3E, and 4E, the metal H3O0 is etched away leaving the metal silicide film 501, and then a nitride film 202 is deposited on each of the layers. A photolithographic mask 30, 1 for forming a contact hole is formed.

Then, as shown in FIGS. 2G, 3F, and 41:, the nitride film 202 is selectively etched to form the base electrode contact hole 72. Contact hole 7 for T-mitter electrode
0 and collector electrode contact hole 71. After forming the resistance pattern contact hole 72 and the wiring pattern contact hole 73, base electrode wiring 91. is formed using a low resistance metal such as AU. Emitter electrode part! 92 and collector electrode arrangement 1193. Other electrodes Ii! A line 94 is formed respectively.

FIG. 5 is a plane pattern diagram of a transistor clamped with SB[) manufactured in this way. As shown in the figure, the emitter region 80, the polysilicon film 601 connected to the base electrode 91, and the metal silicide membrane 50
1 is essentially determined by the mask dimensions,
Unlike the conventional case, the protruding portion of the electrode wiring is not included, so the distance can be made smaller than the conventional distance shown in FIG. Not only does the base resistance become smaller by that amount,
Conventional p+ type external base layer 52 (several tens of Ω/mouth ~ 100
Low non-resistance metal silicide ll60 instead of Ω/mouth)
1 (several Ω to several tens of Ω) is used, so it is small.

Furthermore, since the p-type external base region 52 is not used and the base region 60 itself is slightly smaller, the base-collector capacitance is also reduced, and the frequency characteristics of the transistor are improved.

Further, wiring and resistor formation using SBD and polysilicon films 602 and 603 are formed in the conventional manner without additional steps in the manufacturing process of the present invention.

Note that the edges of the collector-base and base-emitter junctions on the wafer surface are protected with PSG 401, and roughly coated with nitride m20 as a coating when forming contact holes.
2 was used because the oxide film 105.2 was used as the opening. This is because the openings in the PSG film 401 are used, and therefore the nitride film 20
The hole in 2 should be slightly larger than the hole in PSGII401.

[Effects of the Invention] As described above, the present invention provides a semiconductor device having a Schottky barrier diode, in which a silicon film is formed that is connected to a part of the guard ring layer of the Schottky barrier diode and extends to the isolation region. , part of the base region is covered with metal silicide, forming a Schottky barrier diode.

The guard ring layer is formed on the silicon film, and the base electrode is formed on the metal silicide film on the silicon film, so the distance between the base electrode extraction region and the emitter region can be shortened and the base resistance can be reduced. Since no external base layer is provided, the base-collector capacitance can be reduced, and an SBD-clamped semiconductor device with good frequency characteristics can be obtained.

Furthermore, since the resistor formation and the wiring forming process are performed simultaneously in the manufacturing process, there is no additional manufacturing process and the manufacturing process is simplified.

[Brief explanation of drawings]

Figure 1 is a circuit diagram of an npn transistor clamped with an SBD. FIGS. 2A to 2G are cross-sectional views showing the main process steps of a manufacturing method according to an embodiment of the present invention. FIGS. 3A to 3F are cross-sectional views showing the main process steps of forming a resistor using polysilicon. FIGS. 4A to 4F are cross-sectional views showing the main manufacturing process steps for forming interconnects using polysilicon. FIG. 5 is a plan pattern diagram of a transistor manufactured according to an embodiment of the present invention. FIGS. 6A to 6E are cross-sectional views showing the main process steps of a conventional method for manufacturing a semiconductor device. FIG. 7 is a plan pattern diagram of a conventional semiconductor device. In the figure, 1 is a transistor, 2 is a Schottky barrier diode, 10 is a p-type silicon substrate, 30 is an n-type epitaxial layer, 60 is a base region, 61 is a guard ring layer, 80 is an emitter region, 91 is a base electrode, 92
1:1 emitter electrode, 93 a collector electrode, 94 another electrode wiring, 102 a 1111 oxide film, 501 a metal silicide film, and 601, 602, and 603 silicon films. In each figure, the same reference numerals indicate the same or corresponding parts.

Claims (5)

[Claims] (1) A semiconductor device including a semiconductor element clamped by a Schottky barrier diode, comprising: a collector region of a first conductivity type formed on one principal surface of a semiconductor substrate surrounded by an isolation region; and within the collector region. A second surface is formed with an exposed surface.
a conductive type base region; a conductive type base region formed with a main surface exposed in the collector region; one side surface in contact with the separation region; and a second region connected to the base region so as to surround the Schottky barrier diode formation region. a second conductivity type guard ring layer; a first conductivity type emitter region formed with an exposed surface in the base region; and a first conductivity type emitter region connected to at least a portion of the guard ring layer and extending onto the separation region. a second silicon film formed simultaneously with the first silicon film in the wiring and resistance region; a collector electrode connected to the collector region; and a collector electrode connected to the emitter region. an emitter electrode formed on a portion of the base region, a portion of the guard ring layer, the second silicon film, and a Schottky barrier diode formation region formed in the collector region; forming a Schottky barrier diode with the formation region, and a metal silicide film formed on at least both ends of the second resistor silicon film for wiring and the second silicon film for resistor; and a metal silicide film formed on the first silicon film. A semiconductor device comprising: a base electrode formed on the metal silicide film formed on the second silicon film; and wiring and resistance electrodes formed on the metal silicide film on the second silicon film. (2) The semiconductor device according to claim 1, wherein the silicon film is a polycrystalline silicon film. (3) A method for manufacturing a semiconductor device including a semiconductor element clamped by a Schottky barrier diode, the method comprising forming a second conductivity type layer on one main surface of a semiconductor substrate to constitute a collector region surrounded by an isolation region. a first step, a part of the surface of the collector region of the first conductivity type layer is in contact with the base region of the second conductivity type and the isolation region on one side and the Schottky barrier diode formation region is surrounded; a second step of forming a guard ring layer connected to the base region; a first silicon film connected to at least a portion of the guard ring layer and extending above the isolation region; and a resistor formation region; a third step of forming a second silicon film in the wiring formation region; and forming a second silicon film on the surface of the first conductivity type layer including on the base region and the guard ring layer, and on the first and second silicon films. a fourth step of forming a silicon oxide film thereon; selectively etching the silicon oxide film to form a part of the base region above the electrode lead-out portion of the collector region and the emitter region formation portion of the base region; , a fifth step of removing the silicon oxide film on the Schottky barrier diode formation region in the collector region, on the guard ring layer, and on the first and second silicon films; After covering the Schottky barrier diode formation region, the guard ring layer, and the first and second silicon films with a resist film, an electrode extraction portion of the collector region and the emitter region formation portion are formed. a sixth step of implanting a first conductivity type impurity at a high concentration, and performing annealing after removing the resist film to form an emitter region and a collector electrode extraction layer;
above the emitter region, above the collector electrode extraction layer,
and forming a metal silicide film on a portion of the base region, the Schottky barrier diode formation region, the guard ring layer, and the first and second silicon layers,
a seventh step of forming a Schottky barrier diode with the metal silicide film and the first conductivity type layer in the Schottky barrier diode forming region; and performing each of the steps above the isolation region and surrounded by the isolation region. A nitride film is formed in the resistor formation region and the wiring formation region, and a base electrode is formed on the first silicon film and a base electrode is formed on the emitter region through openings provided in the nitride film, respectively. An eighth step of forming an emitter electrode, a collector electrode on the collector electrode extraction layer, and resistor and wiring electrodes on the second silicon film. (4) The first and second silicon films are polycrystalline silicon films, and in the third step, a polycrystalline silicon film is formed on the entire upper surface, and after introducing impurities of the second conductivity type, patterning is performed. 4. The method of manufacturing a semiconductor device according to claim 3, wherein the remaining portion extends from part of the base region to the isolation region in contact with the base region. (5) The openings in the nitride film located on the emitter region and the collector electrode extraction layer in the eighth step are each made larger than the openings in the silicon oxide film at the corresponding locations. A method for manufacturing a semiconductor device according to item 3 or 4.