JPS6038794A - Sense amplifying circuit - Google Patents

Abstract

PURPOSE:To operate a sense amplifying circuit stably in a high speed by detecting a potential change of the common source of a flip flop of the sence amplifying circuit to control the start of main amplification. CONSTITUTION:The sense amplifying circuit consists essentially of the FF constituted with FETs T11 and T12 which amplify minute storage information read onto a bit line. When a potential at the time when initial amplification of a node N13 of the common source of this FF is completed is detected, a detecting circuit CH impresses the second activating signal phiB to the second gate G2. Then, the potential of a node 11 which is precharged to the high level through the gate G2 is held as it is, and a node 12 precharged to the low level has an earth potential, and main amplification is started. Consequently, the start of main amplification is controlled at intervals of an optimum time without delay in distinction from a circuit where the gate G2 is controlled by a fixed timing, and the sense amplifying circuit is operated stably in a high speed.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a sense amplifier circuit, and more particularly to a sense amplifier circuit whose main component is a flip-flop that amplifies minute storage information read onto a bit line. The following explanation uses an N-channel MOf'! Do it with T. However, in circuit terms, the P-channel MO8T and even bipolar transistors are essentially the same.

A conventional sense amplifier circuit of this type has a first gate for performing initial amplification of minute storage information in response to a first control signal supplied from the outside, and a first gate for performing initial amplification of minute storage information in response to a first control signal supplied from the outside. and a second gate for performing main amplification of the minute storage information in response to the second control signal 611+, which is intended to ensure stable and high-speed operation of the circuit.

FIG. 1 shows an example of a conventional sense amplifier circuit used in an MO8 dynamic RAM, which is a 5V single power supply IC, along with all and some memory cells and reference cells. In Figure 1, enhancement g
MO8T (hereinafter referred to as EMO8T) Ts and capacitor C
1 is a 1-bit memory cell, and EMO8T Ta
and capacitor C2 respectively form a reference cell.

h: MOT Tl, Tl, Tl, T4. T7 and Ta
amplifies minute storage information from the memory cell appearing between nodes Nu and N2.

Amplification begins with the first activation signal - EMO8 from the outside.
The second activation signal ct3m is applied to the gate of TTa for initial amplification, and then the second activation signal ct3m is applied to the gate of TTa.
8T Apply to the gate of T4 and increase by 1 + [C to perform 2
It uses a step method.

Kone has performed Ikinashi main amplification, EMO8T
This is to prevent the operation from becoming unstable due to variations and fluctuations in the characteristics of T i , T 2 and +rs.

In such a conventional 4jq configuration, the time + dl interval from the first activation signal φ to the second activation signal -B is identified by an external circuit; Since the initial amplification speed changes due to variations in the transistor characteristics of the EMO8T Ti and Tl that form the flip-flop km and the EMO8T Ts that functions as a gate for initial amplification, the initial amplification speed changes from the first activation signal flJA to the second activation signal In many cases, the optimal time interval to signal 511B cannot be obtained, and there are drawbacks as shown below. In other words, when the initial amplification speed decreases due to variations in the transistor characteristics of the OEMO8T in the sense amplifier circuit, the node N where the minute memory information of the memory cell is output.
EMO8T T4 is activated and main amplification is performed before the initial amplification of the minute difference signal between L and N2 is completed. Malfunctions such as decreased performance may occur.

Also, for the same reason, when the initial amplification rate increases,
After completion of the initial amplification of the minute difference signals at the nodes N1 and N2, the main amplification t- starts after a delay time longer than necessary, which slows down the amplification operation.

An object of the present invention is to detect the potential change sound of the common north of the flip-flop in the sense amplifier circuit and use the potential change to start the main amplification, thereby enabling stable and high-speed operation of the sense amplifier circuit t- It is about providing.

The circuit of the present invention is a sense amplifier circuit whose main component is a flip 70 tube that amplifies minute memory information read out on a pit line, in response to a first control signal ta supplied from the outside. A first gate for performing all the initial amplification of the minute storage information, and a potential of the common north contact of the Noritub flop at the initial amplification start stage are detected, and when the potential reaches a predetermined value, a second control signal is sent. The feature is that a potential detection circuit for outputting the output voltage and a two-gate gate for main amplifying the minute storage information in response to the second control signal are provided.

Next, the present invention will be explained in detail with reference to the drawings.

Referring to FIG. 2 f1:
The first gate Gl inputs the potential of the node N13, which is the common north of the knob, the first activation signal lc, the precharge signal 121P, and the potential of the node N13, and outputs the second activation signal io. detection circuit CI (and
It includes a second activation signal g6o and a second gate (G2) whose input is the potential 1 of the node Nxn. 1st game)
Q 1 and 2nd game) G2 and h, -ttl sof'1+i,
Figure 1 shows Okel EMU 8 T T s and the same configuration as T4.

To explain the basic operation in FIG. 2, first, the precharge signal -P changes from low level to high level, and E M (JS 1' T
16 and TXT are active ratioed and each other's source node Nl
1 and N1ce are precharged, and the precharge signal (EM08T T15 with lip as the gate input is the drain node N15iGNL), and the detection circuit is reset. In this description, it is assumed that the capacitor C1l has a capacitance twice that of the capacitor Cxx, and that the node N14 maintains a high level, as in the conventional circuit shown in FIG.

After the initial operation is completed, the precharge signal -P remains at a low level, then the word signal 121WL changes from a low level to a high level, and EMO8T T13 and T14 whose gate input is the word signal 1WL are activated. is,
The drain node Nll of E~I 08 T T 13 and the source node N14 and the drain node Nxz of EMO8T T14 and the source node Nl11 are respectively electrically connected.

The potential of the node Nll, which was precharged to a high level by the precharge signal -P, remains at a high level because the node N14 is at a high level, and the potential of the node Nll, which is precharged to a high level by the precharge signal gjp, remains at a high level. The potential of Nxx is set to a high level, which is slightly lower than the potential of the node Nil because the node Nzs is connected to GND or is pulled down to a high level that is slightly lower than the potential of the node Nil.
and N12.

Subsequently, the first activation signal 12Ic supplied from the outside changes from a low level to a high level, and the first activation signal 12Ic, which receives the first activation signal -C as an input, operates and forms a flip-flop. Initial amplification of the sense amplifier circuit is performed by gradually lowering the potential of node N13, which is the common source of EMO8T Tll and Txx. As the potential at the node N13 decreases, the potential difference between the nodes N1t and N12 increases, and at this time, the potential t at the node N13, which is a measure of the progress of the increase, is detected by the detection circuit CI.

When the detection circuit CH detects the potential (predetermined) at the node N13 where initial amplification is completed, the second activation signal -
The signal is output to the second gate (G2) to start the main amplification operation.

2nd game) By activating G2, the potential difference between the potential of node N1m (high level) and the potential of node Nxx (high level lower than node N11O) is further expanded, and the potential of node Nil maintains a high level gold. However, the potential of the node N12 becomes GND, and the amplification of the information stored in the memory cell is completed.

The embodiment shown in FIG. 2 and the conventional circuit shown in FIG. 1 are different from each other in that the common north potential of the Noritub flop is lowered using the first gate Gl and the second gate Gz to perform the amplification operation. Although it is common, in this Jibushi Reri, the second goo)
Second activation signal 930 to G2 By detecting the common source potential of the 7 lip-flops inside the t-sense amplifier circuit and using the detected output as an equalizer, the optimum time interval from the start of initial amplification to the start of main amplification can be determined. T? It has a function that conventional circuits do not have, which is to generate electricity.

Figure 3 is the first example of the embodiment shown in Figure 2.)G
1. A circuit example of the detection circuit CH and the second gate (G2) is shown. EMO8T T2 (l and Txe are respectively the first gate) Gl and the second gate G2 constitute 4゛1q, and the other parts constitute the detection circuit Cut.

First, when the precharge signal -P is applied, E M
L) 8 T T x s conducts and releases the potential at node N16? When the first activation signal -C changes from low level to high level, the first activation signal tijct changes from low level to high level.
The EMOS T T 20 serving as the gate input is activated, and the potential of the node N13, which is the common source of the EMO8TTll and Txz forming the flip-flop, is gradually lowered to perform initial amplification.

At this time, FdMO8T T21. T211. Tzs.

T24. The detection circuit CI is composed of Tz s, Tz a, Tz t and T2g, and a capacitor C2X.
EMO8T with first activation signal φC as gate input
When T24 and T2S are activated, the operation starts. At the initial point in time when the first activation signal φC changes from low level to high level, node N15) EMO which performs ia division
S T T 21 , T 22 .

Each potential division node N18°N of T23 and 'fxa
19 Oyohi N 20 Ha EMOS 'ro threshold v
T It is a high level that exceeds all, and city 6 of node N20
E M 08 T T z s, which uses the signal as the gate input, is activated. As a result, S h M 08 T
T28 drain/node N17iGND.

First activation signal IzlCt - EM0 as gate input
8T T2 has an EM which is precharged to the node N ta (t-high level and whose gate input is the potential of the node Nus).
O8T Tzy is activated, but since EMO8T T28, which connects node NIT to the drain, is activated, node N17 maintains GND=i.

Due to the activation of E M 08 T T x o, the node N1
When the potential at node N20 decreases and the initial amplification is completed, the potential at node N20
The potential becomes a low level below the threshold value VT. Therefore, EM08'K" Tz with the potential of node Nzo as the gate input
sldmM, the drain node N17 of FIMO8T T0n becomes high level, and main amplification is started by activating EMO8T Tj19 which uses the potential of node N17 as a gate input. Activated power EM O8T
By T29, the potential at the node N13 becomes GND, the potential at the node Nxx remains at a high level, and the potential at the node N12 becomes GND, completing the amplification of the information stored in the memory cell.

According to the present invention, by adopting the above-mentioned method, the activation signal for the main amplification is generated in the sense amplifier circuit (B)-, so that the initial amplification and the main amplification due to variations and fluctuations in transistor characteristics are generated. By automatically compensating for deviations from the optimal value of the time interval between
Additionally, the external activation signal for the main amplification, which was required in conventional circuits, is no longer required, simplifying the peripheral circuitry.

[Brief explanation of the drawing]

FIG. 1 shows a conventional example, FIG. 2 shows an embodiment of the present invention, and FIG. 3 shows a detailed view of the embodiment. Tl~To, Tz x~Tx t, Tz o~TII
e...Engineering/sment type MO8T (EMO
8T), Ch, Ch, Csx, Cx! , C21...
・・Capacitor, N1~Nll, Nu 1-vNl t
----8 nodes, G1...1st gate, Gx
...Second goo), Ctl...Detection circuit, -P...Precharge signal, φWL...
...Word signal! 21A, sc...first activation signal, φB, 121D...second activation signal. Hayabusa 1 Figure ψ2 Ne 2 Figure N, J *3 eyes

Claims (1)

[Claims] In a sense amplifier circuit whose main component is a flip-flop that amplifies minute memory information read out onto a bit line, initial amplification of the minute memory information is performed in response to a first control signal supplied from the outside. a potential detection circuit that detects the potential of the common source contact of the flip-flop and outputs a second control signal when the potential reaches a predetermined value; A sense amplifier circuit, characterized in that the sense amplifier circuit is provided with a second gate for performing main amplification of the minute storage information.