JPS6038862A - Semiconductor device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

Detailed Description of the Invention [Technical Field] The present invention relates to a technology that is particularly effective when applied to semiconductor technology and also to semiconductor devices in which a 0-M2S (combinmental MO8) logic circuit can be formed. −
The present invention relates to a technique that is effective when used to form elements in a semiconductor integrated circuit device that includes an MO8 logic circuit and a bipolar transistor in the same substrate.

[Background technology]

In a semiconductor device in which a 0-MO8 logic circuit is formed, a p-channel and an n-channel are used to form the 0-MO8 logic circuit.
To form a MO8tO8 field effect transistor with two types of channels, a well of opposite conductivity type to the semiconductor body is formed. Then, one MO8 field effect transistor is formed in that well. For example, in order to form a p-channel MOSN, a field effect transistor, and an n-channel MOS field effect transistor on an n-type semiconductor substrate, a p-type well is formed in the region where the n-channel MO8t field effect transistor is formed. There must be. The two types of MO8tO8 field effect transistors formed in this way are 0-MO8.
Configure a logic circuit.

However, in the MO8 logic circuit formed as described above, a pnp type S thyristor is parasitic between the two types of MO8 field effect transistors constituting the logic circuit. When this parasitic thyristor is triggered by, for example, pulse noise that enters the input terminal band from the outside, the 0-MO8 logic circuit enters a kind of latch-up state, causing the power to be cut off, for example. 7, it will be in a state of constant conduction that will not recover. In some cases, the semiconductor integrated circuit device may be damaged. Such a latch amplifier phenomenon is particularly likely to occur in an input buffer circuit that is directly connected to an input terminal.

In order to avoid the latch amplifier phenomenon described above, it is necessary to prevent the parasitic thyristor from being triggered. It is necessary to space the transistor formation regions sufficiently apart from each other.This reduces the current amplification factor of the two equivalent bipolar transistors of the npn type and pnp type that make up the parasitic thyristor, making it difficult to cause a trigger. I can do it.

However, the above-mentioned solution means 0-MO8
This involves an increase in the layout area for configuring a logic circuit, and is contrary to the demands for higher integration density of semiconductor devices and reduction in semiconductor chip size.

The inventors of the present invention have clarified the above-mentioned problems and provide means for solving such problems.

[Purpose of the invention]

An object of the present invention is to provide a semiconductor technology that can reliably prevent latch-up of c-MOS logic circuits without sacrificing integration density.

The above-mentioned and other objects and novel features of the present invention will be clearly understood from the description of Specification 1 and the accompanying drawings.

[Outline of the invention]

K) A brief overview of typical inventions disclosed in this application is as follows.

That is, by interposing a separation layer between the formation regions of the MO8 field effect transistors constituting the 0-MO8 logic circuit, it is difficult to trigger the parasitic thyristor between the MO8 field effect transistors. This achieves the objective of effectively preventing latch-up without increasing the layout area.

〔Example〕

Hereinafter, typical embodiments of the present invention will be described with reference to the drawings.

In addition, the same or corresponding parts are indicated by the same reference numerals in the drawings.

FIG. 1 shows an embodiment of a semiconductor device according to the present invention.

First, an overview of the semiconductor device shown in the figure will be described.

The semiconductor device shown in the figure is configured as a logic semiconductor integrated circuit device in which a large number of active elements are formed. The figure particularly shows the <=-M os logic circuit portion that constitutes the input buffer circuit of the semiconductor integrated circuit device.

Next, a detailed explanation will be given based on FIG. 1.

The semiconductor integrated circuit device, a part of which is not shown in FIG.
The n-type epitaxial layer 12 (used for ffi, p-type semiconductor substrate) 0 is doped with n-conductivity type impurities at a low concentration. A thick field oxide film 18 and a surface oxide film 2o formed by LOCOS (local oxidation) are formed on the surface of the evitagital layer 120.

Here, in the epitaxial layer 12, a p+ type isolation layer 16 is formed by selectively diffusing p type conductive impurities at a high concentration to reach the substrate 10Vc. This separation layer 1
A pair of MO8s forming a 0-MO8 logic circuit by
Formation regions Ap and A of t-field effect transistors Qp and Qn
A separation region is formed that gaseously separates the n from each other.

Between the epitaxial layer 12 of each formation region Ap and All and the semiconductor substrate 10, an n++ buried layer 14 in which n-type conductive impurities are diffused at a high concentration is formed, respectively. This buried layer 14 functions to increase the conductivity of each of the formation regions Ap and An due to the high concentration of n-conductivity type impurities.

A gate oxide film 20a as an insulating film is formed thinly on the surface of one formation region Ap, and on this branching film 20a, A
A gate electrode 30 made of 1, polycrystalline silicon, or the like is formed. On both sides of this gate electrode 300, a p+ type scattering layer 2 is formed by selectively diffusing n conductivity type impurities at a high concentration.
424 are formed respectively. The diffusion layers 24 and 24 are respectively connected to the drain Dp region and the source sp of the p-channel MOS'Ft field effect transistor Qp.
form an area. In this way, a p-channel MO8 field effect transistor Qp is formed in one formation region Ap.

In addition, the other formation area A n VC is the entire area K
A p-type well is also formed. This p-type well 22 is formed by selectively diffusing n-conductivity type impurities to a low concentration. In the other formation region where this p-type well 22 is formed, the surface texture of An is the gate oxide 1 (λ
A gate electrode 30 made of polycrystalline silicon or the like is formed on this oxide film 20a. On both sides of the goo electrode 30, an n+ type scattering layer 2626 is formed by selectively diffusing an n type conductive impurity to a high concentration. And the diffusion layer 26゜2
6 are each n-channel MOS? ff, forming the drain Dn region and hysode Sn region of the field effect transistor Qn. In this way, n
A channel MO8 electric red effect transistor Qn is formed.
I'm here.

As described above, the p-channel MO8 field effect transistor Qp and the n-channel MO8 field effect transistor Qn are formed with V:t being mutually different from each other. Then, the aluminum wiring 40 is used to take out the electrodes and to form a 0-MOS logic circuit.

That is, as shown in FIG.
, Q, n) Gp, Gn are commonly connected to the input terminal pin, which is also connected to the source Sp of the p-channel MO8 field effect transistor Qp and the 11-channel M
OS @, drain D + of field effect transistor Qn
1 is connected to the drain Dp of the p-channel MOS field effect transistor Qp and the n-channel MO
8 Field effect transistor Q, source Sn of n is connected to power supply V
By connecting the MO8 logic circuit (inverter) to the reference It, the MO8 logic circuit (inverter) is configured to function as an input buffer circuit.

Here, FIG. 3 shows an equivalent circuit of a parasitic thyristor formed between two formation regions Ap and An constituting the 0-Mos logic circuit.

The parasitic relay resistor is isometrically composed of a pnpffi bipolar transistor Qpp and an npniQ bipolar transistor Qnn, and the drain on the p-chi tunnel MO8ffi field effect transistor Qp side I) is composed of a p+ type scattered layer 24n- type epitaxial layer forming a p region. 12, p-
The type well 22 and the source Sn region of the n-channel MOS field effect transistor Qp are formed by a pnpn type structure with an n+ type diffusion layer 26.

Here, a trigger voltage is applied 71 between the base and emitter of either one of the equivalent transistors Qpp or Qnn.
0, and when this trigger voltage exceeds a certain threshold, the collector current of one transistor Qpp supplies the base current of the other transistor O', and the collector current of the other transistor Qnn supplies one of the transistors. Supplying the base current of the transistor 1, this stops 1
A latch-up state occurs, which is the same state as when n-return occurs and a through current flows through the MO8 logic circuit.

However, in the J-MO5 logic circuit of the above-described embodiment, the separation layer 16 is interposed between the two equivalent transistors Qppw and Qnn of the parasitic thyristor, as if it were a diode in a reverse bias state.

As a result, the base of one transistor Qpp and the collector of the other transistor Qnn are electrically isolated, and the positive feedback loop formed by both transistors Qppw and Qnn is interrupted. Alternatively, the positive feedback loop becomes difficult to form. As a result, latch-up can be made less likely to occur.

Furthermore, in the above embodiment, an n++ buried layer 14 was formed in each of the formation regions AI) and An of the MO8t field effect transistors Qp and Qn to increase conductivity.
This buried layer 14 is the equivalent transistor Qppt Qn
Equivalent resistance R connecting each base and emitter of n in parallel
Each functions to lower the sO value. As a result, a state is formed in which the base currents of the respective equivalent transistors Qpp and Qnn are likely to be bypassed, making it even more difficult for the positive feedback state, ie, launch-up, to occur as described above.

Incidentally, even if the buried layer 14 is provided in only one of the formation regions, it is quite effective in preventing the parasitic thyristor from being triggered.

FIG. 4 shows another embodiment of the invention.

First, to explain the differences from the embodiments described above, in the embodiment shown in the figure, a bipolar transistor Qb is formed together with the logic circuits 0 to MO8 described above. Bipolar transistor Qb is p+ type isolated Ji16
A p-type diffusion layer 50 forming a base B region is selectively formed in the element formation region Ab which is separated into island-like portions by heating. It is formed by selectively forming the type scattering layer 52. Further, in the formation region Ab of the bipolar transistor Qb, an n++ buried layer 14 is formed to lower the collector resistance.

In this way, when the above-mentioned 0-MO8 logic circuit is formed together with the bipolar transistor Qb, the buried layer 14 for making it difficult to cause latch-up is replaced by the buried layer 14 for reducing the collector resistance of the bipolar transistor Qb. It will be formed in the same process. As a result, a semiconductor integrated circuit device in which the 0-MO8 logic circuit is formed together with a bipolar transistor can be provided with a structure that is effective in preventing latch-up without increasing the number of steps.

FIG. 5 shows an embodiment of the planar layout of an O-MOS logic circuit having the configuration for preventing launch-up described above.

In the figure, two types of MO8 TV field effect transistors Qp and Qn constituting an O-MOS logic circuit have their common gates Gp and Gn connected to an input terminal pad Pin via an Al wiring 40. First, the source Sp of the -1p channel MO8t field effect transistor Qp and the drain Dn of the field effect transistor Qn are connected to θ and led to the internal logic circuit.

Here, there is a separation between the formation region Ap of the p-channel field effect transistor Qp and the formation region An of the n-channel field effect transistor Qn.
(5 is involved.

In this case, the separation layer 16 has two formation regions Ap, A
p does not necessarily have to be completely isolated.

For example, as shown in FIG. 5, simply forming an electrical barrier that partially blocks the gap between two regions Ap and An inhibits the formation of a positive feedback loop for generating a latch amplifier. , This makes it possible to obtain a sufficient effect of preventing lasodia knob.

〔effect〕

(1) Two types of MUS that make up the 0-MO8 logic circuit
By interposing an isolation region between each formation region of the field effect transistor, the positive feedback path for causing latch-up is electrically separated, or the positive feedback loop is difficult to form. The effect is that latch-up can be reliably prevented without increasing the layout area.

(2) In addition, by forming a buried layer to increase conductivity in the formation region of the MOS field effect transistor constituting the 0-MO8 logic circuit, the base and emitter of the equivalent transistor constituting the parasitic zyristor can be It is possible to lower the parallel resistance value between the two, which has the effect of making latch-up even more difficult to occur.

(3) Additionally, by forming bipolar transistors together with 0MO8 logic circuits.

The buried layer to prevent launch-up from occurring can be formed at the same time as the buried layer to lower the collector resistance of the bipolar transistor, and thereby the latch-up prevention function can be obtained without increasing the number of steps. You can get the effect that you can.

The invention made by the present inventor has been specifically explained above based on examples, but it goes without saying that this invention is not limited to the above examples and can be modified in various ways without departing from the gist thereof. Nor. For example, in addition to the separation layer formed by highly concentrated diffusion of conductive impurities, the separation region is
It can also be constructed with mechanical grooves formed by etching.

[Application field]

The above explanation has mainly been about the case where the invention made by the present inventor is applied to the input buffer circuit technology of a logic semiconductor integrated circuit device, which is the field of application that forms the background of the invention. It can also be applied to, for example, output buffer circuits or internal circuit formation techniques in logic semiconductor integrated RLT circuit devices. MO8 electric field effect formed in the well even with a small tx!・0~M OS logic circuit with transistor as one element is rj
Applicable to those with lH and tL filter conditions.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of a main part of a logic semiconductor integrated circuit device according to the present invention, FIG. 2 is a circuit diagram of the portion shown in FIG. 1, and FIG. 3 is a parasitic thyristor formed in the device of FIG. FIG. 4 is a sectional view showing the main part of another embodiment of the semiconductor integrated circuit device for logic according to the present invention, and FIG. 5 is a plan view of the main part of the semiconductor integrated circuit device according to the invention. FIG. 3 is a diagram showing an example of a layout state. DESCRIPTION OF SYMBOLS 10...p-type semiconductor substrate, 12...n-type epitaxial layer, 14...n+ type buried layer, 16...minute 1
lit region (p”fff separation layer), 18 ・Locos (
sound branching film), 20... surface oxide film, 20a.
・・Insulating FA (lithic acid IHI film), 22...p-
' type well, 24...n+ type expansion layer, 26...p+
Type diffusion layer, 30...gate' electrode, 40...aluminum wiring, 50...p! (νKuixin layer, 52...
・n'' type scattered layer Qp...p channel MOS M; rising ff4 transistor, Ql+...n channel MO
3D Yl-effect-! 47 transistor, Q b... bipolar transistor, I) p, D n-drain, G
p, G n - gate, Sp, Sn... source,
E... Emitter, B... Pace, 0 CoVta, Ap
...Formation region of p-channel MO8I field effect transistor, An...Formation region of ngu-yang, le MO8tW effect transistor, Ab...Formation region of bipolar transistor, Pin...Fluid terminal vanod. .

Claims (1)

[Claims] 1. A complementary insulated gate field effect transistor is provided in a semiconductor substrate, and an n-channel insulated gate field effect transistor and an n-channel insulated gate constitute the complementary insulated gate field effect transistor. 1. A semiconductor device characterized in that an electrical isolation region is interposed between each formation region of a type field effect transistor. 2. Claim 1, characterized in that a buried layer for increasing conductivity is formed in the formation region of at least one of the n-channel insulated gate field effect transistor and the n-channel insulated gate field effect transistor. 1. Semiconductor device described in Section 1. 3. The semiconductor device according to claim 1 or 2, wherein a bipolar transistor is formed together with a complementary insulated gate field effect transistor.