JPS6039927A - Josephson decode circuit - Google Patents

Abstract

PURPOSE:To simplify the circuit and to attain high operation speed by constituting plural complementary signal generating circuits inputting respectively individual signals, an output generating circuit outputting the sum and an NOT circuit of the output with Josephson elements. CONSTITUTION:In inputting input signal A1...An respectively to the complementary signal generating circuits Q1...Qn comprising Josephson JS elements, the signals A1...An and their NOT logic signals A1...An are outputted from the circuits Q1...Qn. The sum circuit S1 inputting the A1,A2...An and outputting a sum signal C1, the sum circuit S2 inputting the A1,A2...An-2,An-1,An and outputting a sum signal C2, the sum sircuit S3 inputting the A1,A2...An-2,An-1,An and outputting the sum signal C3, the sum circuit Sa-1 inputting the A1,A2... An-1,An and outputting a sum signal Ca-1(a=2<n>), and the sum circuit Sa inputting the A1...An and outputting the sum signal Ca are constituted by the JS elements. In inputting the output of the sum circuits S1...Sa to the NOT circuits N1...Na comprising the JS elements, signals B1...Bn comprising the product of the signals A1...An and their NOT signals are outputted from the output of each NOT circuit.

Description

[Detailed Description of the Invention] The present invention takes A1, A, ......A n as input, and B+ = A+ A+ ---An −+ An,
B)=A+A,...A11-4~A
n, B+ =A+ A+...A n-
2) '△1, -1△, 1, B4 =AIA+...
...Δ11-2~An-1~80, Ba-+-~
A1~Δl ”'”'”'~A n -I A n
, Ba-~A1~A2......~An-+~
A logical product of n (however, a=26 and ~Δ1
A Josephson decoding circuit configured using a Josephson element that outputs an output signal expressed as (i = 1.2...a.) represents the negative logic of A1) Regarding the improvement of

As such a Josephson decoding circuit, one having the configuration described below with reference to FIG. 1 has been proposed.

However, for the sake of simplicity, the case of 11-3 and therefore a-23-8 will be described.

That is, a complementary signal generation circuit A+ which takes A1 as an input and outputs A and ~A1, and a complementary signal generation circuit A+ which takes A2 as an input and outputs A2 and ~A1.
Complementary signal generating circuit Q2, which outputs A2, etc., and complementary signal generating circuit Q, which takes A3 as input and outputs A and ~A3, are effective.

In this case, each of the complementary signal generating circuits Q+, h and Q+ is constructed using a Josephson element.

Also, the Josephson elements El+, Fl 1 , E+1 and E? I have I.

Thus, the control lines of Josephson elements Eu and E+i are connected in series, and complementary signal generation circuit Q1 is connected to them.
A1 from J is supplied.

Further, the control lines of the Josephson elements Eit and E++ are connected in series, and are supplied with the signal A1 from the complementary signal generating circuit Q1.

Further, the junctions of the Josephson elements [+1 and Elf are connected in series and -C1 are supplied with A2 from the complementary signal generating circuit Q2.

Further, the junctions of the Josephson elements [+1 and [++] are connected in series and are supplied with ~.DELTA.2 from the complementary signal generating circuit Q2.

Furthermore, Josephson element [+, E+...
...has E.

Thus, the control lines of the Josephson elements E1 and E2 are connected in series and connected to both ends of the junction of the Josephson elements [++ via the resistor R''+2, and the control lines of the Josephson elements E3 and E4 are connected in series. 'f11 line is connected in series, and a resistor R34 is connected across the junction of the Josephson element Ea+.
connected via.

Furthermore, the control lines of Josephson elements E5 and E@6 are connected in series and connected to both ends of the control line junction of Josephson element E5B via a resistor R5i, and the control lines of Josephson elements E5 and E@ The control lines of are connected in series,
A resistor R++ is placed across the junction of the Josephson element E+i.
connected via.

Also, Josephson elements E+, El, Ei and F7
are connected in series, and a complementary signal generation circuit ('
l) Person 3 from r is being supplied.

Furthermore, the Josephson elements E+, Ei, Ei and E
i are connected in series, and a complementary signal generating circuit Q is connected to them.
3 to A3 is supplied.

Also, Josephson element E+, E)...
・Both ends of the junction of E8 are resistors R,, R,...
...Load M+, M2... via R+
......11 is connected.

The above is the configuration of the conventionally proposed di-sefson de-de circuit.

According to such a configuration, the complementary signal generation circuit Q+,
By inputting A1, A2 and At supplied to Q+ and Q, B+ = A+ A) A3 B2-Δ, A1~Δ3 B+ = A+ ~A+A+ B4=A+ ~A2~△3 B5-~△+A+A+ B6-~A+A+~△3 B7 =~A1~ArAr B1-~A1~A2-.A3 Expression No. 11 expressed by the logical product are respectively 0-load M+, lVh, IVh, Mi, IVIs 1.
It can be supplied to MI, MI and MI.

Now, the operation is applied to the load M,13. An example of the case where is supplied is as follows.

In other words, the Josephson element E 1 is also used for A1 and A2 obtained from the complementary signal generation circuits Q and Q2.
1 transitions from a voltage-applied state to a zero-voltage state, and Δ+A+ is generated from both ends of the Josephson element E12 junction.
, and the output A+ At
, A obtained from the complementary signal generating circuit Q3, and the junction of the Josephson element E1 transitions from the incline voltage state to the right voltage state, so that from both ends of the Josephson element [1, B1 -Δ+A+A+ logic output is obtained,
By the operation of supplying it to the load M1, it is possible to supply an output represented by B+ -At At At to the C1 load M1.

However, in the case of the conventional Josephson decoding circuit shown in FIG. 1, the Josephson elements E12, El 1 ,
Since the stage made up of EI N and E++ and the stage made up of Josephson elements E+, EI...Ei are connected in cascade, the Josephson decoding circuit is The overall structure was complicated and large, and the inductance of the wiring between stages caused problems such as inability to operate at high speeds.

The present invention therefore proposes a novel Josephson decoding circuit which does not suffer from the above-mentioned drawbacks, as will be apparent from the detailed description in conjunction with FIG.

FIG. 2 shows an example of the Josephson decoding circuit according to the present invention, and then shows the construction of the following.

That is, with A1 as input, A, and ... A1, A2 as input, 'c, A+ and -A2, An as input point,
A complementary signal generation circuit Q+ configured using a Josephson element, which outputs A n and ~Δ, 1, respectively;
(h......Turn Qn to the right.

In addition, complementary signal generation circuits Q+, Q+...
..."AI from Q n, ~A2......~An -1 and U
”・Δ, 1 is input and the sum output C1 is,
~A+, ~A2......~Δ. -1 and A
With n as input, their sum output C7 is ~Δ+, ~A2''・”'...', ~An-2
, A Tl-+, ~A, 1 as input, their sum output C1 is ~・A1, ~Δn..., ~A
n-2, A11-1 and A11 as input, their sum output C1 is A1, A2......An-
+ and ~An as inputs, their sum output Ca-+(
However, a=2).

AI, A)......Summing circuit S+, St, Sl, Sa configured using Josephson elements, which takes An-+ and An as input and outputs their sum output Ca, respectively.・・・・・・・・・
...Sa-+, turn Sa to the right.

Further, the sum output C1 from the sum circuit S1 is inputted, and the sum output C1 from the sum circuit S is inputted, and the sum output C7 from the sum circuit S is inputted, and the sum output C2 is the sum output from the sum circuit S8. Ca is input, and its negative output D8 is output signal RB I N B I ......
・N+, f'h configured using a Josephson element, which outputs B=1 ・・・・・・・・・
- An example configuration of the Joseph Sonde circuit according to the present invention is 1 degree or more separated from NF1 to the right.

According to such a configuration, the inverting circuits N+, N2, N3.
......Output signals B+, B), B+, B+, obtained from Na-+ and Na, respectively
...Ba-+ and BQ are respectively [:3l-A1△+ ”・”' ”・80 −+ A
11, B2=/”z AI −−−An −+ ~An
, B+=A+ △+ ”・”'”'Δn-2~AII
−I An, Bi =A+ Ay ---An −
2-A1. −+ ~An.

Ba −+ −~At =A2−−−~An−+ An
, Ba-~Δ1~A2 ......~An-
It is clear that this can be obtained as No. 15 expressed by the logic of t~8□.

Therefore, the Josephson decoding circuit according to the present invention shown in FIG. 2 provides the same decoder function as the conventional Josephson decoding circuit shown in FIG.

However, in the Josephson decoding circuit according to the present invention shown in FIG. stage, inverting circuit N+, N+...
The number of cascaded stages does not increase as the value of n increases.

Therefore, according to the Josephson decoding circuit according to the present invention shown in FIG. It has the characteristics of being able to be made small and simple, and also capable of high-speed operation.

Furthermore, in the Josephson decoding circuit according to the present invention shown in FIG. 2, the sum circuits S+, S2...
...As Sa, use a sum circuit like the one shown in Figure 3,
Furthermore, it is possible to use a 1M configuration as shown in FIG. 4 or FIG. 5 as the inverting circuits N+, N2...Na. Furthermore, it can be simplified and miniaturized, and high-speed operation can be achieved.

The summation circuit shown in FIG. 3 will be described below, although a detailed explanation will be omitted.

That is, a resistor 12 is connected between the power supply terminal 11 and the ground.
Josephson elements 13 and 14 are connected in series in that order, and resistor 15 and Josephson element 16 are connected in series in that order.

In addition, the connection midpoint between the resistor 12 and the Josephson element 13,
A resistor 17 is connected between the resistor 15 and the connection midpoint of the Josephson element 16.

Furthermore, a resistor 18 is connected in parallel with the Josephson element 14.

Thus, input terminals TI, T+......T11 are derived from the connection midpoint of Josephson elements 13 and 14 via resistors H+, H+......Hn. Furthermore, the output terminal To is led out from the connection midpoint between the resistor 15 and the Josephson element 16.

The above is shown in FIG. 2 and shows the sum circuits S+, S, .
...Here is an example configuration of a sum circuit that can be applied to Sa.

If J: has such a configuration, i1 detailed explanation will be omitted, but
When there is an input to the input terminals T+, T+...Tn, the Josephson element 1/lh<0 voltage state first transitions to the right voltage state, and then the Josephson element 16 transitions from zero voltage state to right voltage state, then
13 transitions from the zero voltage state to the right voltage state, and as a result,
Output D'; An output is obtained from A-[-0.

Therefore, as shown in Figure 3? 1' 141st 'fIt, table,
Sum circuits S+, St...S used in the Joseonondenide1-de circuit according to the present invention shown in Fig. 2
a, and its configuration is extremely simple.

Therefore, the sum circuit shown in FIG. 3 is similar to the sum circuit shown in FIG.
, S)... Suitable for application to S8.

Further, the NOT circuit shown in FIG. 4 has the following configuration, although detailed explanation will be omitted.

The junction of the Josephson element 22 is connected between the power supply end 21 and the ground, and the junction of the Josephson element 23 and the control line of the Josephson element 24 are connected in series. ing.

Further, a junction of a di,'I Lefson element 22 is connected between the power source end 25 and the ground.

Further, between the power supply terminal 26 and the ground, there is a dielectric between the power terminal 26 and the ground. The junctions of the Fuson elements 2/l are connected.

However, the control line of -C1 Josephson element 22, G3
4! The control line of the Josephson element 23 is connected in series to lead out the C1 input terminal J terminal TI, and the output end To is led out from the side of the junction of the Josephson element 24 opposite to the ground side.

The above is the NOT circuit N1, N, . . . used in the G3 Refson decoding circuit according to the present invention shown in FIG.
. . . This is an example configuration of a sum circuit applicable to Na.

According to such a configuration, although a detailed explanation is omitted, when there is an input to the input terminal TI, the di-Sefson element 23
Since the junction of the However, as the junction of Josephson element 22 transitions from the zero voltage state to the right voltage state, the junction of Josephson element 2/I transitions from the zero voltage state to the voltage state and its As a result, the output terminal TO
The horns coming out of the room are 1!1.

Further, the negative circuit shown in FIG. 5 includes a resistor 32, a junction of the Josephson element 33, and a control line of the Josephson element 34 between the power supply terminal 31 and the ground, although detailed explanation is omitted. The resistor 35 and the junction of the Josephson element 34 are connected in series in that order, and the Josephson element 33 is connected in series in that order.
The input terminal TI is derived from the control line of
The configuration from which lTO is derived is shown on the right.

According to this configuration, although detailed explanation 1 is omitted, when there is an input to the input end TI, the Josephson element 33
The junction of the Josephson element 34 transitions from the zero voltage state to the right voltage state, and therefore the junction of the Josephson element 34 does not transition from the zero voltage state to the voltage state, and therefore the output is not applied to the output terminal To. , when there is no input to the input terminal TI, the junction of the Josephson element 33 does not transition from the zero voltage state to the voltage state, so the junction of the Josephson element 34 transitions from the zero voltage state to the right voltage state, and therefore , an output is obtained at the output terminal To.

From the above, the NOT circuits shown in FIGS. 4 and 5 are similar to the NOT circuits N1, N, . . . N used in the Josephson decoding circuit according to the present invention shown in FIG.
a, and its configuration is extremely simple.

Therefore, the one NOT circuit shown in FIGS. 4 and 5 is replaced by the NOT circuit N+, N+ . It is suitable for application.

[Brief explanation of the drawing]

FIG. 1 is a connection diagram that does not show a conventional Josephson decoding circuit. FIG. 2 is a systematic connection diagram showing the simulator decode circuit according to the present invention. FIG. 1 is a connection diagram showing a summation circuit suitable for application to the summation circuit used in the circuit. FIGS. It is a system diagram showing a negative circuit suitable for application to the circuit. Q+, Q+...Q I+...
. . . Complementary signal generation circuit 31, S+ . . . S.・・・・・・・・・・・・Summary circuit Nl, N+・
・・・・・・・・・N8 ・・・・・・・・・・・・Negation circuit applicant Nippon Telegraph and Telephone Public Corporation Figure 3 Figure 4 Continued from page 1 [Co., Ltd.] Inventor Fuji 1) Osamu - 183 Ono, Atsugi City
Nippon Telegraph and Telephone Public Corporation Atsugi Telecommunications Research within Hata Estate

Claims (1)

[Claims] Ar, AI...... An is used as an input signal,
B1-Δ+ AI・・・・・・An-1Δ11,
B+ = At A2−−−An −+ ~An 1B3
−Δ+ A, ---An −2~An −+ An, B
+ =A+ AI ---An -2~A11-1~A
n, Ba −1=”AI ~A+ −−−−An −+
An, Ba-~Δ, ~A2......~An
-+~△n logical product (however, represents a-2, and ~A
In a Josephson decoding circuit configured using Josephson elements, which outputs an output signal expressed as 1 (1-1, 2...a) represents the negative logic of A1). , A complementarity constructed using Josephson elements, which takes AI as input and outputs A1 and ~A1, takes A2 as input and outputs A2 and ~Δ, and takes An as input and outputs A11 and ~An, respectively. Signal generation circuit Q+, (h...
...Qn, complementary signal generation circuit Q+, Q+ ......
~Δ1, ~Δ, ...... ~△■1-1 and ~ from On
With △11 as input, their sum output C+ i, ~AI
, ~A2......~△1, -4 and Δ. manually, and their sum output C2 is, ~A1, ~△, ......, ~A n -2,
A111, ~A++ as input, their sum output C
+, ~A+, ~A, ......, ~A I
I -2, A Tl i and An are pano j, and their sum output C1 is A+, A+...
With Δ, 1-1 and ~A11 as inputs, their sum output Ca-+ is A+, A2...An-+ and A. Summing circuits S1, B2, B3, B4 are configured using Josephson elements, with the sum output Ca as an input and the sum output Ca as an output, respectively.
5a-1, 8 ports and - Input the sum output IC+ from the sum circuit S1 to its negative output - C+, Input the sum output C2 from the sum circuit S2, and send □ Cr to its negative output, Sum The sum output Ca from the circuit Sa is input, and the negative output Da thereof is output as the j signal B+, B2...B
1. A Josephson decoding circuit comprising a negative circuit N+, N+...Na configured using a Josephson element, which outputs an output as 1.