JPS6041384B2 - Input/output control method - Google Patents

Description

[Detailed Description of the Invention] '1] Technical Field of the Invention The present invention relates to an input/output control method in a data processing system, and in particular, in which multiple paths are provided for selecting an input/output device via a plurality of channel devices. This paper relates to an efficient path selection control method for such input/output systems.

■Technical Background FIG. 1 shows an example of an input/output processing system to which the present invention is directed.

The figure shows three physical channels CHI, CH2, CH3,
Disk devices ○, , D2, and D3, which represent an input/output system composed of six disk devices D, to D6, are coupled to physical channels CH and CH2, while D4,
05,D6 are bonded to CH2 and CH3. As a result, each disk device has two selectable access
will have a pass. The 1/○ super/zizer (10S) that controls input/output in the input/output system treats channel groups CHI and CH2 that can access disk devices D, D2, and D3 as one logical channel LCHI, and performs similar operations. Therefore, physical channels CH2 and CH3 for disk devices D4, Takumi, and D6 are treated as one logical channel LCH2.

Therefore, if paths are equally distributed between LCHI and LCH2, for example to two physical channels under each, the load on physical channel CH2 belonging to both logical channels will be CH3
, and physical channel waits from disk devices that specify a path via CH2 occur frequently due to reasons such as data transfer being in progress, and requests from physical channel CH2 take a longer response time than others. It comes to have.

Therefore, such load imbalance reduces the efficiency of the entire input/output processing. (3) Conventional technology and problems Conventionally, methods such as ROTAE, SEQ, and LCU have been used as input/output path selection methods in input/output systems, but these methods select paths based on the physical configuration of each system. It is about making choices.

Moreover, since the selection method is fixed, it is impossible to cope with load imbalance between paths during actual input/output processing. {4} Object of the Invention The object of the present invention is to provide an input/output control method that equalizes load distribution and dynamically changes path selection order in the above-mentioned input/output system.

'5} Structure of the Invention The present invention achieves the above object by monitoring the response time of each path and feeding it back to the path selection logic. In an input/output system including a device, a plurality of input/output paths provided for each of the plurality of input/output devices, and path selection means, each of the plurality of input/output paths has a pattern representing a selection order of the plurality of input/output paths. a path selection table means constituted by a plurality of entries including a plurality of entries; a pointer means for sequentially changing the position of an entry retrieved from the path selection table means each time an access request to an input/output device occurs; means for controlling the path selection means according to an output path selection order pattern; and means for monitoring the response time of each input/output path to modify and optimize the entry contents of the path selection table means; It is characterized by control to shorten the average response time for path selection.

■ Examples of the invention The present invention will be explained in detail below based on examples.

FIG. 2 shows an embodiment for explaining the function of the path selection table according to the present invention.

In the figure, 1 represents a path selection table for logical channel LCHI, 2 represents a path selection table for logical channel LCH2, and 1', 1'', 2', and 2'' are respectively,
The path selection tape 2 represents the dynamically modified version.

The 1/0 supervisor (10S) performs path selection according to these path selection tables. Each path selection table consists of three entries, and each entry contains two numbers.

The numbers in each of these entries form a pattern for controlling the order of path selection in the input/output system. For example, the first entry (2,1) in table 1 indicates that 10S is disk D. When receiving an access request for D3 to D3, first select CH2 through the logical channel LCHI, and if it is BUSY, select CH2.
This indicates the path selection order instruction to select HI.

The second entry (2,1) in Table 1 indicates that when the 10S next accepts an access request using LCHI,
Referenced. Similarly, the third entry is referenced in the next access request, and the first entry is returned again. The path selection table 2 for LCH2 also performs exactly the same function as the tape loop. The patterns of each entry in Table 1 and Table 2 are all set to give an instruction to select CH2 first.

Therefore, as the operation of the input/output system progresses, the load becomes particularly concentrated on CH2. Therefore, pattern modification for optimization, which will be described later, is performed. Table 1' or 2' is a modification of the pattern of the first entry of table 1 or 2, respectively, so that the path selection order is reversed.

Thereby, the load on CH2 can be reduced.
This correction process is performed in tape loop or 2 condition.
It monitors the average response time of each path and takes action if it becomes too long. Table 1'' or 2'' is a modification in which the pattern of the second entry is reversed when the load is still in an unbalanced state with the pattern of table 1' or 2'. The example shown in Figure 2 above is a case where the number of entries in each path selection table is 3 and the number of pattern elements is 2, but if the number of entries is further increased, even finer control can be performed. It is.

If the number of elements in the pattern is 3 or more, that is,
If three or more physical channels are included in one logical channel, the best pattern may be selected as the modification pattern. Furthermore, since paths with many failures are often retried by hardware, the response time is extended, and the selection order is gradually lowered, making it difficult to be selected.

In other words, this method can be considered to be resistant to path failures. FIG. 3 is a block diagram of an input/output system according to an embodiment of the present invention.

In the same figure, 3 is a processing device, 4 is CHI, and 5 is CH2.
, 6 is CH3, 7 to 9 are disk devices D,, D2, .
..., Dn.

Further, 10 is an input/output control unit by 10S, 11 is its path selection function unit, 12 is a path selection table for logical channel LCHI, 13 is its pointer, 14 is a path selection table for logical channel LCH2, and 15 is its pointer. ,
Reference numeral 16 indicates a response time monitoring section that monitors the average response time and access frequency for each path, and 17 indicates a path selection table modification processing section. The input/output control unit 1 receives a request for access to a disk device from a user and performs program control necessary for input/output processing such as CCW setting.

At this time, the path selection function unit 11 selects the path selection table 1.
2 or 14, path selection is performed using the method described in FIG. Reference to the table is made only for the entry pointed to by pointer 13 or 15. Pointers 13 and 15 move the pointer position one by one each time a table reference is made so that all entries in the table are sequentially referenced.

The response state monitoring unit 16 checks the SIO command issue time and completion time for each path, and calculates the response time and SIO command difference.
Stores data on the number of IO commands issued.

The path selection table correction processing section 17
Based on the response state data of each path stored in 6, an optimization routine performs processing to modify tables 12 and 14.

The optimization routine algorithm is as follows. ■ Based on response state data, create a path ordering pattern with the lowest average response time (best pattern).

■ For each entry in the path selection table, search for one entry that has a pattern opposite to the best pattern (worst pattern) or a pattern close to it.

■ Replace the entry found in ■ with the best pattern in ■.

Note that the path selection table modification process is activated when the load imbalance between paths exceeds a certain level, but it may be activated periodically.

t7} Effects of the Invention As described above, according to the present invention, the algorithm used for input/output path selection is unrelated to the physical configuration, so it is easy to adapt to changes in the system configuration and is dynamic. Since the load on each input/output path can be equalized, the processing efficiency of the entire system can be improved.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a configuration diagram of an input/output system to which the present invention is applied, FIG. 2 is a functional explanatory diagram of an embodiment of a path selection table, and FIG. 3 is a configuration diagram of an input/output system according to an embodiment. It is.

In the figure, 1, 1', 1'' and 2, 2', 2'' are
3 is a processing unit, 4 to 6 are channels, 7 to 9 are disk devices, 1 is an input/output control unit, 11 is a path selection function unit, 12 and 14 are path selection tables, 13 , 15 represents a pointer, 16 represents a response state monitoring section, and 17 represents a path selection table modification processing section 17, respectively.

Na’4 Dimension Z diagram Figure 3

Claims (1)

[Claims] 1. In an input/output system having a plurality of input/output devices, a plurality of input/output paths provided for each of the plurality of input/output devices, and a path selection means, the selection order of the plurality of input/output paths is determined. path selection table means constituted by a plurality of entries each containing a pattern representing a pattern; pointer means for sequentially changing the position of an entry to be read from the path selection table means each time an access request to an input/output device occurs; means for controlling the path selection means according to an input/output path selection order pattern of the input/output path selected entries; and means for monitoring the response time of each input/output path to modify and optimize the entry contents of the path selection table means. An input/output control method characterized in that the input/output control method is controlled to shorten the average response time of input/output path selection.