JPS6041385A - Time switch circuit - Google Patents

Abstract

PURPOSE:To reduce the operating power of a storage circuit and improve a high multiplexity of switches by supplying data successively to storage elements designated with a scanning signal in a channel device of an exchange. CONSTITUTION:D type FFs 10-13 are cascaded circularly to constitute a scanning signal transmitting circuit 1, and outputs (d)-(g) of these FFs are changed in accordance with the rise of a clock signal (b). Latch circuits 20-23 of a storage circuit 2 store input data (b) successively in accordance with this change to generate outputs (m)-(q). After held successively in latch circuits 30-33 of a multiplexer circuit 3 with storage function in accordance with a frame pulse (a), these outputs (m)-(g) are selected successively by a multiplexer 34 in accordance with control information (h)-(l) from a control memory 4 and are transmitted successively through a latch circuit 35.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to an improvement in a time switch circuit used as a main part in a communication path device of a digital exchange.

[Prior art]

As is well known, a time switch is used in a communication path device of a digital exchange, and has a function of performing time-division exchange instead of changing the temporal order of input data.As a conventional example of this type, An example of this is a "time switch circuit" (Japanese Patent Application No. 57-150310) filed separately by the present applicant, which has the configuration shown in FIG.

That is, A, B, C, and D of input data Din are sequentially accumulated in the shift register 000, and then stored in the latch circuit 20 in the multiplexer 2000 with memory function.
10 in parallel and sent from the control memo 1J3000 to the multiplexer 2020.
After selecting the content to be held, for example, C, D, A, B are output as output data Dout via the latch circuit 2030.
It will be sent out based on the ranking. Therefore, since the input data A, B, C, and D are sent out in any order (based on the control information), the temporal order can be swapped.

Note that in this configuration, the exchange speed is determined by the operating speed of the shift register 1000, and the memory is used to determine the exchange speed.
At this time, an advantage arises in that high-speed operation is realized compared to the November switch.

However, the storage operation of input data in the shift register 1000 is performed by all of the storage elements constituting each stage of the shift register 1000 operating at the same time, so operating power is consumed in all stages of the shift register 1000. However, if a high multiplicity time switch that exchanges a large amount of input data is realized using this configuration, the scale of the shift register 1000 will increase with the multiplicity, and the operating power will increase accordingly. In order to increase the speed, the disadvantage arises that the operating power of the MFfn must be increased.

That is, to increase the multiplicity by n times, shift register 100
Both the size and operating speed of 0 must be increased by n times, and the operating power at this time will be n2 times, and due to the increase in power consumption required for operation, such a configuration will not be possible due to advances in integrated circuit technology. Even if the degree of integration is improved, there is a drawback that it is extremely difficult to realize a switch with high multiplicity.

[Summary of the invention]

The present invention has an object of fundamentally eliminating the drawbacks of the conventional technology, and has the following object: to replace the conventional data storage shift register with a scanning signal sending circuit such as a circular shift register and a plurality of storage elements. Using a memory circuit based on K, only the memory elements specified by the scanning signal sent from the scanning signal sending circuit
The present invention provides an extremely effective time switch circuit which sequentially stores data, reduces the number of storage elements whose states are reversed during data storage, and achieves a reduction in operating power.

〔Example〕

The present invention will be described in detail below with reference to FIG. 2 showing an embodiment.

FIG. 2 is a block diagram showing the first embodiment.

In this example, a four-multiplex time switch is shown, but it goes without saying that the present invention can be applied to time switches with any multiplicity.

In the figure, 1 is a circular shift register used as a scanning signal sending circuit;
)10-13 are cascaded in a circular manner.

That is, the output Q of DFFC10 is the input D of DFFC11.
It is connected to I, and the following is the same, and DFFC
The output Q of the DFFC 13 is connected to the input DI of the DFFC 10, and the output Q of each DFFC is sent out cyclically in the 71st order as a scanning signal. 2 is a storage circuit consisting of latch circuits 20 to 23 to which scanning signals from DF'F'C10 to 13 are supplied to respective clock inputs C, 3 is a multiplexer with a storage function, and 4 is a control memory with a storage function. The attached multiplexer 3 selects the data held by the latch circuits 30-33 and the launch circuits 30-33 which hold the data held by the latch circuits 20-23 according to the timing specified by the frame pulse FP. It consists of a multiplexer 34 that selectively and sequentially transmits data according to control information from the control memory 4, and a launch circuit 35 that holds the output of the multiplexer 34.

FIG. 3 is a timing chart showing the operating status of FIG.
Output of FFC10 (a)'t'H' (high level),
DIi”FCl Outputs (e) to (9'L of 1 to 13)
' (low level). Note that this can be easily realized using the well-known preset and preclear functions, which are omitted in the figure. In addition, in these DFFCs 10 to 13, when the clock signal (b) is s(, ", the state of the data input DI is taken into the master and held by the slave, and when ◆I(" The state is held by the master and captured by the slave1), and the outputs (d) to ('I) of DFF'CI O~13 are the rising edge of the clock signal (b). It changes depending on the situation.

In this case, the input data multiplexed on the time side ((riA
,B,C,B7>! According to this order, AI, Bl, CI, DI are given in series, and in the first frame F1, AI, Bl, CI, DI
, A2. in the second frame F2. B2. C2, B2, 3rd
In frame F3, A3. B3. If given as (
Since the scanning signals (d) to (2) are sequentially shifted in synchronization with the signal (b), the scanning signals (d) to (2) are shifted in the second cycle T2 Ti,l: m
L” IH “1L” “1L”, “L” in the third cycle T3
” 'L''II'L", in the fourth cycle T4'
Then, in the first cycle TI of the second frame F2, it is returned to the initial value, and this is warped every four cycles.Therefore, in the first frame F1, The storage circuit 2 receives the data A1 only from the latch circuit 20 in the first cycle T1, and in the second cycle T
In cycle T3, all data CI is received only by the launch circuit 22, and in the fourth cycle T3, all data CI is received only by the launch circuit 22. In cycle T4, only the latch circuit 23 receives the input data 9, and when the scanning signal becomes 1L" after one cycle has passed, each input data is held, and this is repeated every four cycles thereafter.

Therefore, the latch circuit 20 transfers the data A to the latch circuit 20.
1 takes in data B, the latch circuit 22 takes in data C, and the latch circuit 23 takes in data D"k every 4 cycles and holds them. As a result, input data (c) is stored n times, and output 6Tl). (n)(p)(q) occurs.

- On the other hand, the latch circuits 30 to 33 that respond to the frame pulse (a) FP tic are connected to the launch circuit 20 as described above.
23 takes in the retained data, holds it for one frame period, produces outputs (r) to (u), and repeats this process. Information (h) (j) (b) (4 in the first cycle T1 of each frame %L++ % Lrt % I, II
% HNl In the second cycle T2, % Lff 嘱L+
'%H#%V, 3rd cycle T3 TU%L“
“H”Hayabusa L IT◆L”, Hayabusa Hn in the 4th cycle T4
Assuming that Juku L"Hayabusa7.LjHayabusaL11, the multiplexer 34 receives the input 03.02.00.0 according to this signal.
1 is sequentially selected and data D, C, A, and B are sequentially sent out via the latch circuit 35.

In this case, when comparing the maximum operating power consumed by the conventional data input shift register and the scanning signal sending circuit 1 and memory circuit 2 in FIG. 2, the state in each cycle TI-T4 in FIG. The number of memory elements that change is two in the scanning signal sending circuit 1 and one in the memory circuit 2, which reduces the operating power to 3/4 compared to four in the conventional configuration. .

Therefore, even if a time switch with arbitrary multiplicity is configured based on FIG. 2, the number of memory elements that consume operating power during a cycle is two in the scanning signal sending circuit 1 and one in the memory circuit 2. In a multiplexed switch, the operating power consumption is reduced to 3/n of the conventional switch, and the effect of power reduction becomes greater as the scale increases.

Note that although FIG. M2 shows an example in which one memory circuit 2 and one multiplexer 3 with memory function are used, a plurality of memory circuits 2 and multiplexer 3 with memory function may be used together. .

FIG. 4 is a block diagram showing the second embodiment, including a memory circuit 2-1, 2-2, and a multiplexer with memory function 3-1.
．． 3-2, a scanning signal output path 1, and a control memory 4.The memory circuit 3-1.3-2 includes a common scanning signal output circuit 1, and a common control memory. 4 and 4 are subjected to the same control as in FIG. 2, and one data bit and the other bits can be changed in parallel.

FIG. 5 is a block diagram showing the third embodiment, which includes a memory circuit 2-1, 2-2, a multiplexer with memory function 3-.
1.3-2 is controlled by a scanning signal sending circuit 1° and two control memos 1J4-1.4-2. In this case, two The time switch is realized using a common scanning signal sending circuit 1.

In this case, a memory circuit 2-1 is formed by a plurality of memory element groups.
．． When considering the maximum operating power consumed in the data input section when 2-2 or the like is configured, it is generally assumed that there are n times M, and a memory circuit consisting of m groups of memory elements is used.
The time switch constructed in 71 is composed of m×1 memory registers and n-stage circular shift registers, but in the conventional structure, m pieces of n-bit shift registers are used.
The number of memory resistors that consume 1υ operating power is shown in Figures 4 and 5.
According to the configuration shown in the figure, it is clear that the number of m-1-2 is 1, which is much smaller than the conventional mxn. MO8 with a lot of configuration
It is also conceivable to use a circumferential circuit or COD using technology, and the above embodiment is merely an example.

As described above, the present invention is not only applicable to time switches having arbitrary multiplicity of p1, but also significantly reduces power consumption compared to the conventional one. When you scale up your configuration.

In order to avoid a decrease in operating speed due to an increase in the scale of a multiplexer, as described in the above-mentioned patent application (Patent Application No. 57-150310), small-scale multiplexer modules with memory functions are cascaded in a tree-like manner and in multiple stages. The same configuration can be used to achieve high speed through pipeline operation.

FIG. 6 fd is a block diagram showing the fourth embodiment. The memory, scanning signal output path 1, memory circuit 2, and control memory 4 are the same as in FIG. 2, but the multiplexer 3 with memory function is , multiplexer modules 301 and 30 with memory functions that have latch circuits added to the input and output ends of a two-person multiplexer.
2,303 are connected in cascade in two stages in a dendritic manner 9, and the input end latch circuits 311 to 314 of the first stage multiplexer modules 301 and 302 have frame pulses (a) FP input error, The output end latch circuits 315 and 316 of the modules 301 and 302 are supplied with a clock signal CLK having an opposite phase to the clock signal (b) CLK, and the input end latch circuits 317 and 318 of the second stage module 303 are given Clock signal (b)
CLK is applied to the output terminal latch circuit 319 of the module 303, and a clock signal CLK of opposite phase is applied to the output end latch circuit 319 of the module 303, so that each of them is driven by these signals.

FIG. 7 is a timing chart showing the operating status of FIG. 6. Similar to FIG. 3, the input data (c) is AI,
Bl, CI, DI~A3, B3, C3
, D3, and if the scanning signal output path 1 also sends out all of the scanning signals (d) to (9) similar to that shown in FIG. The latch circuits 20 to 23 of the circuit 2 capture and hold data. That is, in the first cycle T1 of each frame F1 to F3, the latch circuit 20 captures data A, and in the second cycle T2, data is captured and held. Latch circuit 21
In the third cycle T3, the data C is captured in the latch circuit 22, and in the fourth cycle T3, the data C is captured in the latch circuit 22.
In Cycle T4, the data D is taken into the latch circuit 23 and held, and outputs (E) (N)
(rl) (q) k, these are the frame pulses (a
) FP, each is simultaneously transferred to the input terminal latch circuits 311 to 314 of the first-stage multiplexer module with memory function 301 and 302, and these are outputs 0) to (u).
', and the input data (c) is repeatedly captured every frame.

On the other hand, the operations of the first-stage multiplexers 320 and 321 are executed according to the control signals (h) and (b) sent from the control memory 4, and the output (r ) Output (s) when t, @LP HN
Output (t)ffi, 'H''SH when t, 1H “'L”
'', select output (U) and send it.

Note that the control signals (jX/l) are inverted signals of the control signals (h) and Qc), for example, 0c)(h)tl
-Deaf H"'H", %Ht+ It", %L p
By sending data in the order of @HW and LIFIL#, the data held by the latch circuits 311 to 314 can be sent out in a completely opposite order to the input order. However, this transmission/rank selection is first performed in the first-stage multiplexer modules 301 and 302 with memory function by the control signal (j) (transfer), and also by the control signal (j) (4) in the next cycle. This is performed by the second stage multiplexer module 303 with storage function.

Therefore, the control signals (Ic) and (t) are (h) and (j
) must be supplied with a delay of one cycle, which is twice the period. That is, as shown in FIG. 7, the control signal (h)
is frame pulse (a) synchronized with the rising edge of FP,
And this 1. With a period of /2, ya I
, n are repeated alternately, but the control signal (k) is set so that the falling edge of the frame pulse (a) F P is synchronized with 9, and the period is twice that of the periodic signal (h). HTr
, the latter half is supplied as J, I+. For this reason, the first-stage multiplexer modules 301 and 30 with memory function
2 means that in the first cycle TI of the four cycles T1 to T4 in which the latch circuits 311 to 314 hold data, data B and D of output (s) (u) are output in the next cycle T2. (r) Data A and C of (t) are selected and held by the output end latch circuits 315 and 316, and this is repeated again in the following two cycles T3 and T4, and each of these data is The data is transferred to the input end latch circuits 317 and 318 of the second-stage multiplexer module with storage function 3030, but this timing is different from that of the first-stage multiplexer module with storage function 301,
Output (V) of 302 (→Yoshi is also delayed by one cycle, so
Assuming that the timing matches this, the control signal (j)
, (4 is supplied, the output of the tB latch circuit 318 is supplied in the first two cycles, and the output of the latch circuit 318 is supplied in the next two cycles.
17 is selected by the multiplexer 222 and sent out via the output end latch circuit 319, and the output data (2) which is also sent out from the same module 303 in the second stage.
Dout, C, B, and A are ranked, and data ranking changes and pipeline operations are performed.

In addition, in FIG. 6 as well, lower operating power of the data input section is realized in the same way as in FIG.
A configuration similar to that shown in the figure and lower operating power can also be achieved.

〔Effect of the invention〕

As is clear from the above explanation, according to the present invention, only some of the memory elements constituting the time switch consume all the operating power, and even if the configuration is enlarged, the number of memory elements increases. Therefore, large-scale time switches can be easily realized using integrated circuits, and conventionally, it is possible to perform high-speed operation due to the increase in power consumption. Become. Therefore, it becomes possible to realize a large-scale time switch with sufficiently high speed operation and low power consumption, and a remarkable effect can be obtained in terms of making the time switch more compact and economical.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing a conventional example, Fig. 2 and subsequent figures show embodiments of the present invention, Fig. 2 is a block diagram showing the first embodiment, and Fig. 3 is a timing diagram showing the operation status of Fig. 82. Figure 4 is a block diagram showing the second embodiment. Figure 5 is a block diagram showing the third embodiment. Block diagram showing an example,
FIG. 7 is a timing chart showing the operating status of FIG. 6. 1...Scanning signal sending circuit, 2, 2-1. 2-2...Memory circulation, 3, 3-1, 3-2
...Multiplexer with memory function, 4.4-1゜4-2-...Control memory, 10-13...Intimidation/D'F
FC (D-type flip-flop circuit), 20-23.30
~33,35,311~319 φ...Latch circuit,
34,320-322...Multiplexer. Patent applicant Masaki Yamakawa, agent of Nippon Telegraph and Telephone Public Corporation

Claims (2)

[Claims] (1) A first means for storing serially applied input data according to the order and transmitting the stored contents according to the order specified by externally supplied control information, and supplying the control information to the first means. a scanning signal sending circuit comprising a plurality of storage elements cyclically connected in cascade and sequentially and cyclically sending out a scanning signal from each storage element in synchronization with a tack signal; a memory circuit that includes a memory element provided corresponding to the memory element of the circuit and stores the input data in each memory element in response to the scanning signal; and a memory circuit that stores the input data in parallel with each memory element of the circuit. A time switch circuit characterized in that said first means is provided with a multiplexer with a memory function that holds the held contents and selectively and sequentially selects and transmits the held contents in accordance with said control information. (2) A small-scale multiplexer module with a memory function consisting of a storage element and a multiplexer is connected in multiple stages in a dendritic manner, and each stage is operated in a pipeline.
Is it 't' that a multiplexer with e-memory function is used? A time switch circuit according to claim 1, characterized in that the time switch circuit has the following characteristics: